From: Thor Thayer Date: Wed, 22 Jun 2016 13:58:56 +0000 (-0500) Subject: Documentation: dt: socfpga: Add Arria10 Ethernet binding X-Git-Tag: v4.14-rc1~2814^2~3 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f103ad1556aa985eb094cdfa8a8e4d618732bad2;p=platform%2Fkernel%2Flinux-rpi.git Documentation: dt: socfpga: Add Arria10 Ethernet binding Add the device tree bindings needed to support the Altera Ethernet FIFO buffers on the Arria10 chip. Signed-off-by: Thor Thayer Acked-by: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac Link: http://lkml.kernel.org/r/1466603939-7526-6-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov --- diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt index 15eb0df..b545856 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt @@ -82,6 +82,14 @@ Required Properties: - interrupts : Should be single bit error interrupt, then double bit error interrupt, in this order. +Ethernet FIFO ECC +Required Properties: +- compatible : Should be "altr,socfpga-eth-mac-ecc" +- reg : Address and size for ECC block registers. +- altr,ecc-parent : phandle to parent Ethernet node. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt, in this order. + Example: eccmgr: eccmgr@ffd06000 { @@ -108,4 +116,20 @@ Example: interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, <33 IRQ_TYPE_LEVEL_HIGH> ; }; + + emac0-rx-ecc@ff8c0800 { + compatible = "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0800 0x400>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, + <36 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-tx-ecc@ff8c0c00 { + compatible = "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0c00 0x400>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, + <37 IRQ_TYPE_LEVEL_HIGH>; + }; };