From: Biju Das Date: Fri, 3 Dec 2021 11:51:51 +0000 (+0000) Subject: clk: renesas: r9a07g044: Add GPU clock and reset entries X-Git-Tag: v6.1-rc5~2162^2~7^2^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f0b62b0bbedcdfde18116080605cebd9beec4ee9;p=platform%2Fkernel%2Flinux-starfive.git clk: renesas: r9a07g044: Add GPU clock and reset entries Add GPU clock and reset entries to CPG driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211203115154.31864-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 85132b6..79042bf 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -198,6 +198,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x554, 6), DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, 0x554, 7), + DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, + 0x558, 0), + DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, + 0x558, 1), + DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, + 0x558, 2), DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 0x570, 0), DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, @@ -285,6 +291,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_SPI_RST, 0x850, 0), DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1), + DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), + DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), + DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),