From: Gabe Black <gabeblack@chromium.org>
Date: Mon, 5 Dec 2011 12:09:25 +0000 (+0000)
Subject: x86: Add infrastructure to extract an e820 table from the coreboot tables
X-Git-Tag: u-boot_fixes_v1~277^2~8
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f08fa7a2018495c6f2a5eaba5f6d8fdcbc67e6c6;p=kernel%2Fu-boot.git

x86: Add infrastructure to extract an e820 table from the coreboot tables

Also approximate the size of RAM using the largest RAM address available
in the tables. There may be areas which are marked as reserved which are
actually at the end of RAM.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
---

diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index b56085a..f8fdac6 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -23,13 +23,49 @@
  */
 
 #include <common.h>
+#include <malloc.h>
+#include <asm/e820.h>
 #include <asm/u-boot-x86.h>
+#include <asm/global_data.h>
+#include <asm/arch-coreboot/sysinfo.h>
+#include <asm/arch-coreboot/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	int i;
+
+	unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries);
+	if (num_entries < lib_sysinfo.n_memranges) {
+		printf("Warning: Limiting e820 map to %d entries.\n",
+			num_entries);
+	}
+	for (i = 0; i < num_entries; i++) {
+		struct memrange *memrange = &lib_sysinfo.memrange[i];
+
+		entries[i].addr = memrange->base;
+		entries[i].size = memrange->size;
+		entries[i].type = memrange->type;
+	}
+	return num_entries;
+}
+
 int dram_init_f(void)
 {
-	gd->ram_size = 64*1024*1024;
+	int i;
+	phys_size_t ram_size = 0;
+
+	for (i = 0; i < lib_sysinfo.n_memranges; i++) {
+		struct memrange *memrange = &lib_sysinfo.memrange[i];
+		unsigned long long end = memrange->base + memrange->size;
+
+		if (memrange->type == CB_MEM_RAM && end > ram_size)
+			ram_size = end;
+	}
+	gd->ram_size = ram_size;
+	if (ram_size == 0)
+		return -1;
 	return 0;
 }