From: Krzysztof Parzyszek Date: Mon, 18 Jul 2016 15:47:25 +0000 (+0000) Subject: [Hexagon] Add verbose debugging mode to Hexagon MI Scheduler X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f05dc4d5ddeb15527dab52a35c012449600d798c;p=platform%2Fupstream%2Fllvm.git [Hexagon] Add verbose debugging mode to Hexagon MI Scheduler Patch by Sergei Larin. llvm-svn: 275799 --- diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 61d5f47..b70a6b1 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -18,12 +18,18 @@ #include "llvm/CodeGen/ScheduleDAGMutation.h" #include "llvm/IR/Function.h" +#include +#include + static cl::opt IgnoreBBRegPressure("ignore-bb-reg-pressure", cl::Hidden, cl::ZeroOrMore, cl::init(false)); static cl::opt SchedPredsCloser("sched-preds-closer", cl::Hidden, cl::ZeroOrMore, cl::init(true)); +static cl::opt SchedDebugVerboseLevel("misched-verbose-level", + cl::Hidden, cl::ZeroOrMore, cl::init(1)); + static cl::opt TopUseShorterTie("top-use-shorter-tie", cl::Hidden, cl::ZeroOrMore, cl::init(false)); @@ -289,6 +295,13 @@ void VLIWMachineScheduler::schedule() { assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone."); placeDebugValues(); + + DEBUG({ + unsigned BBNum = begin()->getParent()->getNumber(); + dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n"; + dumpSchedule(); + dbgs() << '\n'; + }); } void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) { @@ -416,8 +429,8 @@ void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpCycle() { } CheckPending = true; - DEBUG(dbgs() << "*** " << Available.getName() << " cycle " - << CurrCycle << '\n'); + DEBUG(dbgs() << "*** Next cycle " << Available.getName() << " cycle " + << CurrCycle << '\n'); } /// Move the boundary of scheduled code by one SUnit. @@ -509,16 +522,38 @@ SUnit *ConvergingVLIWScheduler::VLIWSchedBoundary::pickOnlyChoice() { #ifndef NDEBUG void ConvergingVLIWScheduler::traceCandidate(const char *Label, - const ReadyQueue &Q, - SUnit *SU, PressureChange P) { + const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P) { dbgs() << Label << " " << Q.getName() << " "; if (P.isValid()) dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":" << P.getUnitInc() << " "; else dbgs() << " "; + dbgs() << "cost(" << Cost << ")\t"; SU->dump(DAG); } + +// Very detailed queue dump, to be used with higher verbosity levels. +void ConvergingVLIWScheduler::readyQueueVerboseDump( + const RegPressureTracker &RPTracker, SchedCandidate &Candidate, + ReadyQueue &Q) { + RegPressureTracker &TempTracker = const_cast(RPTracker); + + dbgs() << ">>> " << Q.getName() << "\n"; + for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) { + RegPressureDelta RPDelta; + TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta, + DAG->getRegionCriticalPSets(), + DAG->getRegPressure().MaxSetPressure); + std::stringstream dbgstr; + dbgstr << "SU(" << std::setw(3) << (*I)->NodeNum << ")"; + dbgs() << dbgstr.str(); + SchedulingCost(Q, *I, Candidate, RPDelta, true); + dbgs() << "\t"; + (*I)->getInstr()->dump(); + } + dbgs() << "\n"; +} #endif /// getSingleUnscheduledPred - If there is exactly one unscheduled predecessor @@ -580,14 +615,23 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, MachineInstr *Instr = SU->getInstr(); + DEBUG(if (verbose) dbgs() << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); // Forced priority is high. - if (SU->isScheduleHigh) + if (SU->isScheduleHigh) { ResCount += PriorityOne; + DEBUG(dbgs() << "H|"); + } // Critical path first. if (Q.getID() == TopQID) { ResCount += (SU->getHeight() * ScaleTwo); + DEBUG(if (verbose) { + std::stringstream dbgstr; + dbgstr << "h" << std::setw(3) << SU->getHeight() << "|"; + dbgs() << dbgstr.str(); + }); + // If resources are available for it, multiply the // chance of scheduling. if (Top.ResourceModel->isResourceAvailable(SU)) { @@ -599,6 +643,12 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, } else { ResCount += (SU->getDepth() * ScaleTwo); + DEBUG(if (verbose) { + std::stringstream dbgstr; + dbgstr << "d" << std::setw(3) << SU->getDepth() << "|"; + dbgs() << dbgstr.str(); + }); + // If resources are available for it, multiply the // chance of scheduling. if (Bot.ResourceModel->isResourceAvailable(SU)) { @@ -626,6 +676,12 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, } ResCount += (NumNodesBlocking * ScaleTwo); + DEBUG(if (verbose) { + std::stringstream dbgstr; + dbgstr << "blk " << std::setw(2) << NumNodesBlocking << ")|"; + dbgs() << dbgstr.str(); + }); + // Factor in reg pressure as a heuristic. if (!IgnoreBBRegPressure) { // Decrease priority by the amount that register pressure exceeds the limit. @@ -737,7 +793,11 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, } } - DEBUG(if (verbose) dbgs() << " Total(" << ResCount << ")"); + DEBUG(if (verbose) { + std::stringstream dbgstr; + dbgstr << "Total " << std::setw(4) << ResCount << ")"; + dbgs() << dbgstr.str(); + }); return ResCount; } @@ -750,7 +810,9 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, ConvergingVLIWScheduler::CandResult ConvergingVLIWScheduler:: pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker, SchedCandidate &Candidate) { - DEBUG(Q.dump()); + DEBUG(if (SchedDebugVerboseLevel > 1) + readyQueueVerboseDump(RPTracker, Candidate, Q); + else Q.dump();); // getMaxPressureDelta temporarily modifies the tracker. RegPressureTracker &TempTracker = const_cast(RPTracker); @@ -767,6 +829,7 @@ pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker, // Initialize the candidate if needed. if (!Candidate.SU) { + DEBUG(traceCandidate("DCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -776,7 +839,7 @@ pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker, // Best cost. if (CurrentCost > Candidate.SCost) { - DEBUG(traceCandidate("CCAND", Q, *I)); + DEBUG(traceCandidate("CCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h index 611527e..51c84a4 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h @@ -59,7 +59,7 @@ public: public: VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM) : SchedModel(SM), TotalPackets(0) { - ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI); + ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI); // This hard requirement could be relaxed, // but for now do not let it proceed. @@ -243,7 +243,10 @@ protected: SchedCandidate &Candidate); #ifndef NDEBUG void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, - PressureChange P = PressureChange()); + int Cost, PressureChange P = PressureChange()); + + void readyQueueVerboseDump(const RegPressureTracker &RPTracker, + SchedCandidate &Candidate, ReadyQueue &Q); #endif };