From: mason.huo <mason.huo@starfivetech.com>
Date: Fri, 22 Apr 2022 00:36:34 +0000 (+0800)
Subject: riscv: dts: jh7110: Add syscon support
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f045a8a02e0d848f1b3ed49a6d61a1e092ae8ff5;p=platform%2Fkernel%2Flinux-starfive.git

riscv: dts: jh7110: Add syscon support

Add 'stg', 'sys', 'aon' system control register support,
access these registers through syscon framework.

Signed-off-by: mason.huo <mason.huo@starfivetech.com>
---

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 490ebea..11079cc 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -175,6 +175,21 @@
 			cache-unified;
 		};
 
+		aon_syscon: aon_syscon@17010000 {
+				compatible = "syscon";
+				reg = <0x0 0x17010000 0x0 0x1000>;
+		};
+
+		stg_syscon: stg_syscon@10240000 {
+				compatible = "syscon";
+				reg = <0x0 0x10240000 0x0 0x1000>;
+		};
+
+		sys_syscon: sys_syscon@13030000 {
+				compatible = "syscon";
+				reg = <0x0 0x13030000 0x0 0x1000>;
+		};
+
 		clint: clint@2000000 {
 			compatible = "riscv,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;