From: cltang Date: Wed, 20 Apr 2011 16:48:28 +0000 (+0000) Subject: 2011-04-20 Chung-Lin Tang X-Git-Tag: upstream/4.9.2~21293 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=efecc03c0cb32c8b83802d6423464dfe3b1e5d54;p=platform%2Fupstream%2Flinaro-gcc.git 2011-04-20 Chung-Lin Tang * config/arm/arm.c (arm_legitimize_reload_address): For NEON quad-word modes, reduce to 9-bit index range when above 1016 limit. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@172779 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 455bfeb..c70cdb6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-04-20 Chung-Lin Tang + + * config/arm/arm.c (arm_legitimize_reload_address): For NEON + quad-word modes, reduce to 9-bit index range when above 1016 + limit. + 2011-04-20 Andrew Stubbs * config/arm/arm.c (arm_gen_constant): Move movw support .... diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 38aa390..46255cb 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -6330,7 +6330,15 @@ arm_legitimize_reload_address (rtx *p, : 0) if (coproc_p) - low = SIGN_MAG_LOW_ADDR_BITS (val, 10); + { + low = SIGN_MAG_LOW_ADDR_BITS (val, 10); + + /* NEON quad-word load/stores are made of two double-word accesses, + so the valid index range is reduced by 8. Treat as 9-bit range if + we go over it. */ + if (TARGET_NEON && VALID_NEON_QREG_MODE (mode) && low >= 1016) + low = SIGN_MAG_LOW_ADDR_BITS (val, 9); + } else if (GET_MODE_SIZE (mode) == 8) { if (TARGET_LDRD)