From: Sai Prakash Ranjan Date: Tue, 18 Aug 2020 14:55:14 +0000 (+0530) Subject: arm64: dts: qcom: sc7180: Fix the LLCC base register size X-Git-Tag: v5.15~2574^2~25^2~68 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=efe788361f72914017515223414d3f20abe4b403;p=platform%2Fkernel%2Flinux-starfive.git arm64: dts: qcom: sc7180: Fix the LLCC base register size There is one LLCC logical bank(LLCC0) on SC7180 SoC and the size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct the size and fix copy paste mistake carried over from SDM845. Reviewed-by: Douglas Anderson Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order") Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node") Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index b0dd859..d3e6008c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2631,7 +2631,7 @@ system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; + reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = ; };