From: Stefan Agner Date: Wed, 18 Nov 2015 02:05:25 +0000 (-0800) Subject: drm/fsl-dcu: specify volatile registers X-Git-Tag: v4.6-rc1~12^2~30^2~7 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=efb8b49196c0cb0723024182e04072abaec96cdf;p=platform%2Fkernel%2Flinux-exynos.git drm/fsl-dcu: specify volatile registers Since we are using cached registers, we need to specify volatile registers explicitly to avoid reading their value from the cache. This allows to read the correct interrupt status in fsl_dcu_drm_irq and clear the asserted bits only. Signed-off-by: Stefan Agner --- diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index 9648b7f..b4e33e3 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -28,11 +28,21 @@ #include "fsl_dcu_drm_crtc.h" #include "fsl_dcu_drm_drv.h" +static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg) +{ + if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE) + return true; + + return false; +} + static const struct regmap_config fsl_dcu_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .cache_type = REGCACHE_RBTREE, + + .volatile_reg = fsl_dcu_drm_is_volatile_reg, }; static int fsl_dcu_drm_irq_init(struct drm_device *dev) @@ -125,7 +135,7 @@ static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg) if (int_status & DCU_INT_STATUS_VBLANK) drm_handle_vblank(dev, 0); - ret = regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0xffffffff); + ret = regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status); if (ret) dev_err(dev->dev, "set DCU_INT_STATUS failed\n"); ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,