From: Bjorn Pettersson Date: Tue, 31 Mar 2020 09:31:53 +0000 (+0200) Subject: [X86] Do not assume types are legal in getFauxShuffleMask X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ef49895da894c56397879e3cb9a03f35d079617a;p=platform%2Fupstream%2Fllvm.git [X86] Do not assume types are legal in getFauxShuffleMask Summary: Make sure we do not assert on value types not being simple in getFauxShuffleMask when analysing operations such as "v8i16 = truncate v8i24". Reviewers: RKSimon Reviewed By: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77136 --- diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 129185a..bda54eb 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7551,7 +7551,11 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts, case ISD::TRUNCATE: case X86ISD::VTRUNC: { SDValue Src = N.getOperand(0); - MVT SrcVT = Src.getSimpleValueType(); + EVT SrcVT = Src.getValueType(); + // Truncated source must be a simple vector. + if (!SrcVT.isSimple() || (SrcVT.getSizeInBits() % 128) != 0 || + (SrcVT.getScalarSizeInBits() % 8) != 0) + return false; unsigned NumSrcElts = SrcVT.getVectorNumElements(); unsigned NumBitsPerSrcElt = SrcVT.getScalarSizeInBits(); unsigned Scale = NumBitsPerSrcElt / NumBitsPerElt; diff --git a/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll b/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll new file mode 100644 index 0000000..7ddc0f1 --- /dev/null +++ b/llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll @@ -0,0 +1,31 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s + +; Verify that we don't crash when compiling this. We used to hit an +; assert like this +; +; llc: ../include/llvm/CodeGen/ValueTypes.h:251: llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed. +; +; due to getFauxShuffleMask not checking that the VT was simple before a call +; to getSimpleValueType(). + +define i1 @dont_hit_assert(i24 signext %d) { +; CHECK-LABEL: dont_hit_assert: +; CHECK: # %bb.0: # %for.cond +; CHECK-NEXT: movb $-1, %al +; CHECK-NEXT: negb %al +; CHECK-NEXT: sete %al +; CHECK-NEXT: retq +for.cond: + %t0 = insertelement <8 x i24> zeroinitializer, i24 1, i32 0 + %t5 = icmp slt <8 x i24> %t0, zeroinitializer + %t7 = icmp slt i24 0, %d + %rdx.shuf = shufflevector <8 x i1> %t5, <8 x i1> undef, <8 x i32> + %bin.rdx = and <8 x i1> %t5, %rdx.shuf + %rdx.shuf22 = shufflevector <8 x i1> %bin.rdx, <8 x i1> undef, <8 x i32> + %bin.rdx23 = and <8 x i1> %bin.rdx, %rdx.shuf22 + %rdx.shuf24 = shufflevector <8 x i1> %bin.rdx23, <8 x i1> undef, <8 x i32> + %bin.rdx25 = and <8 x i1> %bin.rdx23, %rdx.shuf24 + %t8 = extractelement <8 x i1> %bin.rdx25, i32 0 + ret i1 %t8 +}