From: Sagar Ghuge <sagar.ghuge@intel.com>
Date: Wed, 21 Jul 2021 22:24:29 +0000 (-0700)
Subject: intel/compiler: Handle ternary add in lower_simd_width
X-Git-Tag: upstream/22.3.5~19975
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ef29bb6bc53bf07097ddaf6329c8892f50168e7e;p=platform%2Fupstream%2Fmesa.git

intel/compiler: Handle ternary add in lower_simd_width

We need to lower the add3 instruction simd width otherwise in simd32
mode, we endup writing 4 register wide data which is not allowed.

Reported-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>
---

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 6052d37..8499a35 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -7322,6 +7322,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
    case BRW_OPCODE_SAD2:
    case BRW_OPCODE_MAD:
    case BRW_OPCODE_LRP:
+   case BRW_OPCODE_ADD3:
    case FS_OPCODE_PACK:
    case SHADER_OPCODE_SEL_EXEC:
    case SHADER_OPCODE_CLUSTER_BROADCAST: