From: Jessica Paquette <jpaquette@apple.com>
Date: Tue, 23 Apr 2019 18:20:47 +0000 (+0000)
Subject: [AArch64][GlobalISel] Teach regbankselect about G_INTRINSIC_TRUNC
X-Git-Tag: llvmorg-10-init~7201
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ede0b2e69544170ab9d02f349c2b24669fa10793;p=platform%2Fupstream%2Fllvm.git

[AArch64][GlobalISel] Teach regbankselect about G_INTRINSIC_TRUNC

Add it to isPreISelGenericFloatingPointOpcode, and add a regbankselect test.

Update arm64-vfloatintrinsics.ll now that we can select it.

llvm-svn: 359022
---

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index 025f2381..92f6c14 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -406,6 +406,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
   case TargetOpcode::G_FABS:
   case TargetOpcode::G_FEXP:
   case TargetOpcode::G_FRINT:
+  case TargetOpcode::G_INTRINSIC_TRUNC:
     return true;
   }
   return false;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
new file mode 100644
index 0000000..d43d3eb
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
+
+...
+---
+name:            test_f32.intrinsic_trunc
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+frameInfo:
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $s0
+
+    ; CHECK-LABEL: name: test_f32.intrinsic_trunc
+    ; CHECK: liveins: $s0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
+    ; CHECK: [[INTRINSIC_TRUNC:%[0-9]+]]:fpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+    ; CHECK: $s0 = COPY [[INTRINSIC_TRUNC]](s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %0:_(s32) = COPY $s0
+    %1:_(s32) = G_INTRINSIC_TRUNC %0
+    $s0 = COPY %1(s32)
+    RET_ReallyLR implicit $s0
+
+...
+---
+name:            test_f64.intrinsic_trunc
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+frameInfo:
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0
+
+    ; CHECK-LABEL: name: test_f64.intrinsic_trunc
+    ; CHECK: liveins: $d0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
+    ; CHECK: [[INTRINSIC_TRUNC:%[0-9]+]]:fpr(s64) = G_INTRINSIC_TRUNC [[COPY]]
+    ; CHECK: $d0 = COPY [[INTRINSIC_TRUNC]](s64)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %0:_(s64) = COPY $d0
+    %1:_(s64) = G_INTRINSIC_TRUNC %0
+    $d0 = COPY %1(s64)
+    RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll b/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
index 9ea7ba5..16344184 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
@@ -183,12 +183,19 @@ define %v4f16 @test_v4f16.ceil(%v4f16 %a) {
   %1 = call %v4f16 @llvm.ceil.v4f16(%v4f16 %a)
   ret %v4f16 %1
 }
+
+; FALLBACK-NOT: remark{{.*}}test_v4f16.trunc
 define %v4f16 @test_v4f16.trunc(%v4f16 %a) {
   ; CHECK-LABEL:          test_v4f16.trunc:
   ; CHECK-NOFP16-COUNT-4: frintz s{{[0-9]+}}, s{{[0-9]+}}
   ; CHECK-FP16-NOT:       fcvt
   ; CHECK-FP16:           frintz.4h
   ; CHECK-FP16-NEXT:      ret
+  ; GISEL-LABEL:          test_v4f16.trunc:
+  ; GISEL-NOFP16-COUNT-4: frintz s{{[0-9]+}}, s{{[0-9]+}}
+  ; GISEL-FP16-NOT:       fcvt
+  ; GISEL-FP16:           frintz.4h
+  ; GISEL-FP16-NEXT:      ret
   %1 = call %v4f16 @llvm.trunc.v4f16(%v4f16 %a)
   ret %v4f16 %1
 }
@@ -421,12 +428,19 @@ define %v8f16 @test_v8f16.ceil(%v8f16 %a) {
   %1 = call %v8f16 @llvm.ceil.v8f16(%v8f16 %a)
   ret %v8f16 %1
 }
+
+; FALLBACK-NOT: remark{{.*}}test_v8f16.trunc
 define %v8f16 @test_v8f16.trunc(%v8f16 %a) {
   ; CHECK-LABEL:          test_v8f16.trunc:
   ; CHECK-NOFP16-COUNT-8: frintz s{{[0-9]+}}, s{{[0-9]+}}
   ; CHECK-FP16-NOT:       fcvt
   ; CHECK-FP16:           frintz.8h
   ; CHECK-FP16-NEXT:      ret
+  ; GISEL-LABEL:          test_v8f16.trunc:
+  ; GISEL-NOFP16-COUNT-8: frintz s{{[0-9]+}}, s{{[0-9]+}}
+  ; GISEL-FP16-NOT:       fcvt
+  ; GISEL-FP16:           frintz.8h
+  ; GISEL-FP16-NEXT:      ret
   %1 = call %v8f16 @llvm.trunc.v8f16(%v8f16 %a)
   ret %v8f16 %1
 }
@@ -616,8 +630,11 @@ define %v2f32 @test_v2f32.ceil(%v2f32 %a) {
   ret %v2f32 %1
 }
 ; CHECK-LABEL: test_v2f32.trunc:
+; FALLBACK-NOT: remark{{.*}}test_v2f32.trunc
+; GISEL-LABEL: test_v2f32.trunc:
 define %v2f32 @test_v2f32.trunc(%v2f32 %a) {
   ; CHECK: frintz.2s
+  ; GISEL: frintz.2s
   %1 = call %v2f32 @llvm.trunc.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
@@ -786,8 +803,11 @@ define %v4f32 @test_v4f32.ceil(%v4f32 %a) {
   ret %v4f32 %1
 }
 ; CHECK: test_v4f32.trunc:
+; FALLBACK-NOT: remark{{.*}}test_v4f32.trunc
+; GISEL: test_v4f32.trunc:
 define %v4f32 @test_v4f32.trunc(%v4f32 %a) {
   ; CHECK: frintz.4s
+  ; GISEL: frintz.4s
   %1 = call %v4f32 @llvm.trunc.v4f32(%v4f32 %a)
   ret %v4f32 %1
 }
@@ -956,8 +976,11 @@ define %v2f64 @test_v2f64.ceil(%v2f64 %a) {
   ret %v2f64 %1
 }
 ; CHECK: test_v2f64.trunc:
+; FALLBACK-NOT: remark{{.*}}test_v2f64.trunc
+; GISEL: test_v2f64.trunc:
 define %v2f64 @test_v2f64.trunc(%v2f64 %a) {
   ; CHECK: frintz.2d
+  ; GISEL: frintz.2d
   %1 = call %v2f64 @llvm.trunc.v2f64(%v2f64 %a)
   ret %v2f64 %1
 }