From: Wenjing Liu Date: Fri, 15 Oct 2021 16:48:41 +0000 (-0400) Subject: drm/amd/display: fix register write sequence for LINK_SQUARE_PATTERN X-Git-Tag: v6.6.17~8832^2~6^2~6 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=edcf52caa985c010d0a6022190c8e3d3980a0223;p=platform%2Fkernel%2Flinux-rpi.git drm/amd/display: fix register write sequence for LINK_SQUARE_PATTERN [why&how] write LINK_SQUARE_PATTERN_num + 1 for square pulse pattern. Specs requirement to write this register prior to write LINK_QUAL_LANEX_SET. Acked-by: Aurabindo Pillai Signed-off-by: Wenjing Liu Reviewed-by: George Shen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index cc25ba0..cb7bf91 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -5329,6 +5329,14 @@ bool dc_link_dp_set_test_pattern( return false; if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { +#if defined(CONFIG_DRM_AMD_DC_DCN) + if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE) + core_link_write_dpcd(link, + DP_LINK_SQUARE_PATTERN, + p_custom_pattern, + 1); + +#endif /* tell receiver that we are sending qualification * pattern DP 1.2 or later - DP receiver's link quality * pattern is set using DPCD LINK_QUAL_LANEx_SET diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index bc87ea0..e68e9a8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -898,6 +898,9 @@ struct dpcd_usb4_dp_tunneling_info { #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 #endif +#ifndef DP_LINK_SQUARE_PATTERN +#define DP_LINK_SQUARE_PATTERN 0x10F +#endif #ifndef DP_DSC_CONFIGURATION #define DP_DSC_CONFIGURATION 0x161 #endif