From: Thierry Reding <treding@nvidia.com>
Date: Fri, 28 Jun 2019 08:59:19 +0000 (+0200)
Subject: arm64: tegra: Add SOR0_OUT clock on Tegra210
X-Git-Tag: v5.15~4957^2~20^2~10
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ed93a666bb32cb35a0f4c42bf9f63a047a90d475;p=platform%2Fkernel%2Flinux-starfive.git

arm64: tegra: Add SOR0_OUT clock on Tegra210

This clock was not previously used because it is a fixed clock. However,
adding it here allows operating systems to deal with SOR0 the same way
as SOR1.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index d21cf27..a20cd36 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -254,10 +254,11 @@
 			reg = <0x0 0x54540000 0x0 0x00040000>;
 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA210_CLK_SOR0>,
+				 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
 				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
 				 <&tegra_car TEGRA210_CLK_PLL_DP>,
 				 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
-			clock-names = "sor", "parent", "dp", "safe";
+			clock-names = "sor", "out", "parent", "dp", "safe";
 			resets = <&tegra_car 182>;
 			reset-names = "sor";
 			pinctrl-0 = <&state_dpaux_aux>;