From: Dylan Reid Date: Mon, 3 Nov 2014 18:28:56 +0000 (-0800) Subject: ASoC: max98090: Correct pclk divisor settings X-Git-Tag: v3.18~5^2~6^2~1^7 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ece509c10985ba93ccc8c68f808a9e767250041c;p=platform%2Fkernel%2Flinux-exynos.git ASoC: max98090: Correct pclk divisor settings The Baytrail-based chromebooks have a 20MHz mclk, the code was setting the divisor incorrectly in this case. According to the 98090 datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20. Correct this and the surrounding clock ranges as well to match the datasheet. Signed-off-by: Dylan Reid Signed-off-by: Mark Brown --- diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c index d519294..1229554 100644 --- a/sound/soc/codecs/max98090.c +++ b/sound/soc/codecs/max98090.c @@ -1941,13 +1941,13 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, * 0x02 (when master clk is 20MHz to 40MHz).. * 0x03 (when master clk is 40MHz to 60MHz).. */ - if ((freq >= 10000000) && (freq < 20000000)) { + if ((freq >= 10000000) && (freq <= 20000000)) { snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, M98090_PSCLK_DIV1); - } else if ((freq >= 20000000) && (freq < 40000000)) { + } else if ((freq > 20000000) && (freq <= 40000000)) { snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, M98090_PSCLK_DIV2); - } else if ((freq >= 40000000) && (freq < 60000000)) { + } else if ((freq > 40000000) && (freq <= 60000000)) { snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, M98090_PSCLK_DIV4); } else {