From: Andrew Burgess <andrew.burgess@embecosm.com>
Date: Thu, 13 Dec 2018 19:06:23 +0000 (+0000)
Subject: gdb/riscv: Add float status registers to save and restore reggroups
X-Git-Tag: binutils-2_32~269
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ecc82c059059cfa21a8a099779253686f9637f9f;p=external%2Fbinutils.git

gdb/riscv: Add float status registers to save and restore reggroups

We should save and restore the floating point status registers.  This
became an issue when testing 32-bit float on a target with 64-bit with
the gdb.base/callfuncs.exp test.

gdb/ChangeLog:

	* riscv-tdep.c (riscv_register_reggroup_p): Save and restore fcsr,
	fflags, and frm registers.
---

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index ea00361..513bc7c 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,5 +1,10 @@
 2018-12-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 
+	* riscv-tdep.c (riscv_register_reggroup_p): Save and restore fcsr,
+	fflags, and frm registers.
+
+2018-12-22  Andrew Burgess  <andrew.burgess@embecosm.com>
+
 	* riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function.
 	(riscv_gdbarch_init): Register new function with gdbarch.
 	* riscv-tdep.h: New enum to define RISC-V DWARF register numbers.
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 3408f5a..704e851 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -896,7 +896,10 @@ riscv_register_reggroup_p (struct gdbarch  *gdbarch, int regnum,
   else if (reggroup == restore_reggroup || reggroup == save_reggroup)
     {
       if (riscv_has_fp_regs (gdbarch))
-	return regnum <= RISCV_LAST_FP_REGNUM;
+	return (regnum <= RISCV_LAST_FP_REGNUM
+		|| regnum == RISCV_CSR_FCSR_REGNUM
+		|| regnum == RISCV_CSR_FFLAGS_REGNUM
+		|| regnum == RISCV_CSR_FRM_REGNUM);
       else
 	return regnum < RISCV_FIRST_FP_REGNUM;
     }