From: Rhys Perry Date: Mon, 14 Sep 2020 19:58:33 +0000 (+0100) Subject: aco: keep track of temporaries' regclasses in the Program X-Git-Tag: upstream/21.0.0~5245 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ec2185c5984b66fb9cae33bd561cf35096c9861e;p=platform%2Fupstream%2Fmesa.git aco: keep track of temporaries' regclasses in the Program A future change will switch the liveness sets to bit vectors, which don't contain regclass information. Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- diff --git a/src/amd/compiler/aco_builder_h.py b/src/amd/compiler/aco_builder_h.py index a5338ce..5be8c20 100644 --- a/src/amd/compiler/aco_builder_h.py +++ b/src/amd/compiler/aco_builder_h.py @@ -253,23 +253,23 @@ public: } Temp tmp(RegClass rc) { - return (Temp){program->allocateId(), rc}; + return program->allocateTmp(rc); } Temp tmp(RegType type, unsigned size) { - return (Temp){program->allocateId(), RegClass(type, size)}; + return tmp(RegClass(type, size)); } Definition def(RegClass rc) { - return Definition((Temp){program->allocateId(), rc}); + return Definition(program->allocateTmp(rc)); } Definition def(RegType type, unsigned size) { - return Definition((Temp){program->allocateId(), RegClass(type, size)}); + return def(RegClass(type, size)); } Definition def(RegClass rc, PhysReg reg) { - return Definition(program->allocateId(), reg, rc); + return Definition(program->allocateId(rc), reg, rc); } inline aco_opcode w64or32(WaveSpecificOpcode opcode) const { diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index bfab27b..2463ecf 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -390,7 +390,7 @@ void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components) split->operands[0] = Operand(vec_src); std::array elems; for (unsigned i = 0; i < num_components; i++) { - elems[i] = {ctx->program->allocateId(), rc}; + elems[i] = ctx->program->allocateTmp(rc); split->definitions[i] = Definition(elems[i]); } ctx->block->instructions.emplace_back(std::move(split)); @@ -697,7 +697,7 @@ Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1) assert(src.src.ssa->bit_size == 8 || src.src.ssa->bit_size == 16); assert(size == 1); return extract_8_16_bit_sgpr_element( - ctx, Temp(ctx->program->allocateId(), s1), &src, sgpr_extract_undef); + ctx, ctx->program->allocateTmp(s1), &src, sgpr_extract_undef); } RegClass elem_rc = elem_size < 4 ? RegClass(vec.type(), elem_size).as_subdword() : RegClass(vec.type(), elem_size / 4); @@ -711,7 +711,7 @@ Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1) elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc); vec_instr->operands[i] = Operand{elems[i]}; } - Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size / 4)}; + Temp dst = ctx->program->allocateTmp(RegClass(vec.type(), elem_size * size / 4)); vec_instr->definitions[0] = Definition(dst); ctx->block->instructions.emplace_back(std::move(vec_instr)); ctx->allocated_vec.emplace(dst.id(), elems); @@ -739,7 +739,7 @@ void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode o if (instr->no_unsigned_wrap) sop2->definitions[0].setNUW(true); if (writes_scc) - sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1); + sop2->definitions[1] = Definition(ctx->program->allocateId(s1), scc, s1); ctx->block->instructions.emplace_back(std::move(sop2)); } @@ -4427,7 +4427,7 @@ void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr aco_ptr vec(create_instruction(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1)); for (unsigned i = 0; i < instr->dest.ssa.num_components; i++) { - Temp tmp = {ctx->program->allocateId(), v1}; + Temp tmp = ctx->program->allocateTmp(v1); emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask); vec->operands[i] = Operand(tmp); } @@ -5656,7 +5656,7 @@ static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr aco_ptr vec{create_instruction(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)}; for (unsigned i = 0; i < coords.size(); i++) vec->operands[i] = Operand(coords[i]); - Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())}; + Temp res = ctx->program->allocateTmp(RegClass(RegType::vgpr, coords.size())); vec->definitions[0] = Definition(res); ctx->block->instructions.emplace_back(std::move(vec)); return res; @@ -5722,7 +5722,7 @@ void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr) if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr) tmp = dst; else - tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)}; + tmp = ctx->program->allocateTmp(RegClass(RegType::vgpr, num_channels)); load->definitions[0] = Definition(tmp); load->idxen = true; load->glc = access & (ACCESS_VOLATILE | ACCESS_COHERENT); @@ -5743,7 +5743,7 @@ void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr) if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr) tmp = dst; else - tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)}; + tmp = ctx->program->allocateTmp(RegClass(RegType::vgpr, num_components)); bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0; aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip; @@ -6020,7 +6020,7 @@ void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr) glsl_sampler_type_is_array(type)) { assert(instr->dest.ssa.num_components == 3); - Temp tmp = {ctx->program->allocateId(), v3}; + Temp tmp = ctx->program->allocateTmp(v3); def = Definition(tmp); emit_split_vector(ctx, tmp, 3); @@ -9042,7 +9042,7 @@ void visit_phi(isel_context *ctx, nir_phi_instr *instr) Operand src = operands[i]; phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc); } - Temp phi_dst = {ctx->program->allocateId(), rc}; + Temp phi_dst = ctx->program->allocateTmp(rc); phi->definitions[0] = Definition(phi_dst); ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi)); new_vec[k] = phi_dst; @@ -9230,7 +9230,7 @@ static Operand create_continue_phis(isel_context *ctx, unsigned first, unsigned aco_opcode::p_linear_phi, Format::PSEUDO, block.linear_preds.size(), 1)); for (unsigned i = 0; i < block.linear_preds.size(); i++) phi->operands[i] = vals[block.linear_preds[i] - first]; - val = Operand(Temp(ctx->program->allocateId(), rc)); + val = Operand(ctx->program->allocateTmp(rc)); phi->definitions[0] = Definition(val.getTemp()); block.instructions.emplace(block.instructions.begin(), std::move(phi)); } @@ -9384,7 +9384,7 @@ static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond assert(cond.regClass() == ctx->program->lane_mask); aco_ptr branch; branch.reset(create_instruction(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); branch->operands[0] = Operand(cond); ctx->block->instructions.push_back(std::move(branch)); @@ -9425,7 +9425,7 @@ static void begin_divergent_if_else(isel_context *ctx, if_context *ic) /* branch from logical then block to invert block */ aco_ptr branch; branch.reset(create_instruction(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); BB_then_logical->instructions.emplace_back(std::move(branch)); add_linear_edge(BB_then_logical->index, &ic->BB_invert); @@ -9443,7 +9443,7 @@ static void begin_divergent_if_else(isel_context *ctx, if_context *ic) add_linear_edge(ic->BB_if_idx, BB_then_linear); /* branch from linear then block to invert block */ branch.reset(create_instruction(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); BB_then_linear->instructions.emplace_back(std::move(branch)); add_linear_edge(BB_then_linear->index, &ic->BB_invert); @@ -9454,7 +9454,7 @@ static void begin_divergent_if_else(isel_context *ctx, if_context *ic) /* branch to linear else block (skip else) */ branch.reset(create_instruction(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); branch->operands[0] = Operand(ic->cond); ctx->block->instructions.push_back(std::move(branch)); @@ -9485,7 +9485,7 @@ static void end_divergent_if(isel_context *ctx, if_context *ic) /* branch from logical else block to endif block */ aco_ptr branch; branch.reset(create_instruction(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); BB_else_logical->instructions.emplace_back(std::move(branch)); add_linear_edge(BB_else_logical->index, &ic->BB_endif); @@ -9505,7 +9505,7 @@ static void end_divergent_if(isel_context *ctx, if_context *ic) /* branch from linear else block to endif block */ branch.reset(create_instruction(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); BB_else_linear->instructions.emplace_back(std::move(branch)); add_linear_edge(BB_else_linear->index, &ic->BB_endif); @@ -9544,7 +9544,7 @@ static void begin_uniform_if_then(isel_context *ctx, if_context *ic, Temp cond) aco_ptr branch; aco_opcode branch_opcode = aco_opcode::p_cbranch_z; branch.reset(create_instruction(branch_opcode, Format::PSEUDO_BRANCH, 1, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); branch->operands[0] = Operand(cond); branch->operands[0].setFixed(scc); @@ -9578,7 +9578,7 @@ static void begin_uniform_if_else(isel_context *ctx, if_context *ic) /* branch from then block to endif block */ aco_ptr branch; branch.reset(create_instruction(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); BB_then->instructions.emplace_back(std::move(branch)); add_linear_edge(BB_then->index, &ic->BB_endif); @@ -9607,7 +9607,7 @@ static void end_uniform_if(isel_context *ctx, if_context *ic) /* branch from then block to endif block */ aco_ptr branch; branch.reset(create_instruction(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 1)); - branch->definitions[0] = {ctx->program->allocateId(), s2}; + branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->definitions[0].setHint(vcc); BB_else->instructions.emplace_back(std::move(branch)); add_linear_edge(BB_else->index, &ic->BB_endif); @@ -10325,7 +10325,7 @@ static void emit_stream_output(isel_context *ctx, unsigned offset = output->offset + start * 4; - Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)}; + Temp write_data = ctx->program->allocateTmp(RegClass(RegType::vgpr, count)); aco_ptr vec{create_instruction(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)}; for (int i = 0; i < count; ++i) vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u); @@ -10474,13 +10474,13 @@ Pseudo_instruction *add_startpgm(struct isel_context *ctx) unsigned size = ctx->args->ac.args[i].size; unsigned reg = ctx->args->ac.args[i].offset; RegClass type = RegClass(file == AC_ARG_SGPR ? RegType::sgpr : RegType::vgpr, size); - Temp dst = Temp{ctx->program->allocateId(), type}; + Temp dst = ctx->program->allocateTmp(type); ctx->arg_temps[i] = dst; startpgm->definitions[arg] = Definition(dst); startpgm->definitions[arg].setFixed(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256}); arg++; } - startpgm->definitions[arg_count] = Definition{ctx->program->allocateId(), exec, ctx->program->lane_mask}; + startpgm->definitions[arg_count] = Definition{ctx->program->allocateId(ctx->program->lane_mask), exec, ctx->program->lane_mask}; Pseudo_instruction *instr = startpgm.get(); ctx->block->instructions.push_back(std::move(startpgm)); diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 43b1038..7d4c65d 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -1152,7 +1152,7 @@ void init_context(isel_context *ctx, nir_shader *shader) ctx->program->config->spi_ps_input_addr = spi_ps_inputs; for (unsigned i = 0; i < impl->ssa_alloc; i++) - allocated[i] = Temp(ctx->program->allocateId(), allocated[i].regClass()); + allocated[i] = ctx->program->allocateTmp(allocated[i].regClass()); ctx->allocated.reset(allocated.release()); ctx->cf_info.nir_to_aco.reset(nir_to_aco.release()); diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index 9b3f5a3..04c4dd2 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -1561,6 +1561,7 @@ class Program final { public: float_mode next_fp_mode; std::vector blocks; + std::vector temp_rc = {s1}; RegisterDemand max_reg_demand = RegisterDemand(); uint16_t num_waves = 0; uint16_t max_waves = 0; /* maximum number of waves, regardless of register usage */ @@ -1607,12 +1608,18 @@ public: void *private_data; } debug; - uint32_t allocateId() + uint32_t allocateId(RegClass rc) { assert(allocationID <= 16777215); + temp_rc.push_back(rc); return allocationID++; } + Temp allocateTmp(RegClass rc) + { + return Temp(allocateId(rc), rc); + } + uint32_t peekAllocationId() { return allocationID; diff --git a/src/amd/compiler/aco_lower_phis.cpp b/src/amd/compiler/aco_lower_phis.cpp index 923ec8b..f21d954 100644 --- a/src/amd/compiler/aco_lower_phis.cpp +++ b/src/amd/compiler/aco_lower_phis.cpp @@ -76,7 +76,7 @@ Operand get_ssa(Program *program, unsigned block_idx, ssa_state *state, bool bef !(program->blocks[state->phi_block_idx].kind & block_kind_loop_exit)) { return Operand(program->lane_mask); } else { - Temp res = Temp(program->allocateId(), program->lane_mask); + Temp res = Temp(program->allocateTmp(program->lane_mask)); state->latest[block_idx] = Operand(res); Operand ops[pred]; @@ -207,7 +207,7 @@ void lower_divergent_bool_phi(Program *program, ssa_state *state, Block *block, if (phi->operands[i].isUndefined()) continue; - state->writes[block->logical_preds[i]] = program->allocateId(); + state->writes[block->logical_preds[i]] = program->allocateId(program->lane_mask); } bool uniform_merge = block->kind & block_kind_loop_header; diff --git a/src/amd/compiler/aco_lower_to_cssa.cpp b/src/amd/compiler/aco_lower_to_cssa.cpp index a51f61a..4bd1c68 100644 --- a/src/amd/compiler/aco_lower_to_cssa.cpp +++ b/src/amd/compiler/aco_lower_to_cssa.cpp @@ -146,7 +146,7 @@ bool collect_phi_info(cssa_ctx& ctx) progress = true; /* create new temporary and rename operands */ - Temp new_tmp = Temp{ctx.program->allocateId(), phi->definitions[0].regClass()}; + Temp new_tmp = ctx.program->allocateTmp(phi->definitions[0].regClass()); if (is_logical) ctx.logical_phi_info[preds[i]].emplace_back(Definition(new_tmp), op); else diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index c082564..ea60ad1 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -2193,8 +2193,9 @@ bool combine_add_sub_b2i(opt_ctx& ctx, aco_ptr& instr, aco_opcode n } ctx.uses[instr->operands[i].tempId()]--; new_instr->definitions[0] = instr->definitions[0]; - new_instr->definitions[1] = instr->definitions.size() == 2 ? instr->definitions[1] : - Definition(ctx.program->allocateId(), ctx.program->lane_mask); + new_instr->definitions[1] = + instr->definitions.size() == 2 ? instr->definitions[1] : + Definition(ctx.program->allocateTmp(ctx.program->lane_mask)); new_instr->definitions[1].setHint(vcc); new_instr->operands[0] = Operand(0u); new_instr->operands[1] = instr->operands[!i]; diff --git a/src/amd/compiler/aco_reduce_assign.cpp b/src/amd/compiler/aco_reduce_assign.cpp index 301fe80..a1e69a6 100644 --- a/src/amd/compiler/aco_reduce_assign.cpp +++ b/src/amd/compiler/aco_reduce_assign.cpp @@ -95,7 +95,7 @@ void setup_reduce_temp(Program* program) reduceTmp_in_loop |= block.loop_nest_depth > 0; if ((int)last_top_level_block_idx != inserted_at) { - reduceTmp = {program->allocateId(), reduceTmp.regClass()}; + reduceTmp = program->allocateTmp(reduceTmp.regClass()); aco_ptr create{create_instruction(aco_opcode::p_start_linear_vgpr, Format::PSEUDO, 0, 1)}; create->definitions[0] = Definition(reduceTmp); /* find the right place to insert this definition */ @@ -135,7 +135,7 @@ void setup_reduce_temp(Program* program) vtmp_in_loop |= need_vtmp && block.loop_nest_depth > 0; if (need_vtmp && (int)last_top_level_block_idx != vtmp_inserted_at) { - vtmp = {program->allocateId(), vtmp.regClass()}; + vtmp = program->allocateTmp(vtmp.regClass()); aco_ptr create{create_instruction(aco_opcode::p_start_linear_vgpr, Format::PSEUDO, 0, 1)}; create->definitions[0] = Definition(vtmp); if (last_top_level_block_idx == block.index) { diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 675e575..aa35e28 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -549,7 +549,7 @@ void update_renames(ra_ctx& ctx, RegisterFile& reg_file, } } // FIXME: if a definition got moved, change the target location and remove the parallelcopy - copy.second.setTemp(Temp(ctx.program->allocateId(), copy.second.regClass())); + copy.second.setTemp(ctx.program->allocateTmp(copy.second.regClass())); ctx.assignments.emplace_back(copy.second.physReg(), copy.second.regClass()); assert(ctx.assignments.size() == ctx.program->peekAllocationId()); reg_file.fill(copy.second); @@ -1576,7 +1576,7 @@ Temp handle_live_in(ra_ctx& ctx, Temp val, Block* block) Temp tmp = read_variable(ctx, val, preds[0]); /* if the block is not sealed yet, we create an incomplete phi (which might later get removed again) */ - new_val = Temp{ctx.program->allocateId(), val.regClass()}; + new_val = ctx.program->allocateTmp(val.regClass()); ctx.assignments.emplace_back(); aco_opcode opcode = val.is_linear() ? aco_opcode::p_linear_phi : aco_opcode::p_phi; aco_ptr phi{create_instruction(opcode, Format::PSEUDO, preds.size(), 1)}; @@ -1611,7 +1611,7 @@ Temp handle_live_in(ra_ctx& ctx, Temp val, Block* block) /* the variable has been renamed differently in the predecessors: we need to insert a phi */ aco_opcode opcode = val.is_linear() ? aco_opcode::p_linear_phi : aco_opcode::p_phi; aco_ptr phi{create_instruction(opcode, Format::PSEUDO, preds.size(), 1)}; - new_val = Temp{ctx.program->allocateId(), val.regClass()}; + new_val = ctx.program->allocateTmp(val.regClass()); phi->definitions[0] = Definition(new_val); for (unsigned i = 0; i < preds.size(); i++) { phi->operands[i] = Operand(ops[i]); @@ -2335,7 +2335,7 @@ void register_allocation(Program *program, std::vector& live_out_per_bl if (op.isTemp() && op.isFirstKill()) register_file.block(op.physReg(), op.regClass()); } - Temp tmp = {program->allocateId(), can_sgpr ? s1 : v1}; + Temp tmp = program->allocateTmp(can_sgpr ? s1 : v1); ctx.assignments.emplace_back(); PhysReg reg = get_reg(ctx, register_file, tmp, parallelcopy, instr); diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp index 7d3055e..b76805a 100644 --- a/src/amd/compiler/aco_spill.cpp +++ b/src/amd/compiler/aco_spill.cpp @@ -751,7 +751,7 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) } /* variable is spilled at predecessor and live at current block: create reload instruction */ - Temp new_name = {ctx.program->allocateId(), live.first.regClass()}; + Temp new_name = ctx.program->allocateTmp(live.first.regClass()); aco_ptr reload = do_reload(ctx, live.first, new_name, ctx.spills_exit[pred_idx][live.first]); instructions.emplace_back(std::move(reload)); reg_demand.push_back(demand_before); @@ -783,7 +783,7 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) } /* variable is spilled at predecessor and live at current block: create reload instruction */ - Temp new_name = {ctx.program->allocateId(), live.first.regClass()}; + Temp new_name = ctx.program->allocateTmp(live.first.regClass()); aco_ptr reload = do_reload(ctx, live.first, new_name, ctx.spills_exit[pred_idx][live.first]); instructions.emplace_back(std::move(reload)); reg_demand.emplace_back(reg_demand.back()); @@ -944,7 +944,7 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) Temp tmp = phi->operands[i].getTemp(); /* reload phi operand at end of predecessor block */ - Temp new_name = {ctx.program->allocateId(), tmp.regClass()}; + Temp new_name = ctx.program->allocateTmp(tmp.regClass()); Block& pred = ctx.program->blocks[pred_idx]; unsigned idx = pred.instructions.size(); do { @@ -984,7 +984,7 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) continue; /* variable is spilled at predecessor and has to be reloaded */ - Temp new_name = {ctx.program->allocateId(), pair.first.regClass()}; + Temp new_name = ctx.program->allocateTmp(pair.first.regClass()); Block& pred = ctx.program->blocks[pred_idx]; unsigned idx = pred.instructions.size(); do { @@ -1024,7 +1024,7 @@ void add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx) /* the variable was renamed differently in the predecessors: we have to create a phi */ aco_opcode opcode = pair.first.is_linear() ? aco_opcode::p_linear_phi : aco_opcode::p_phi; aco_ptr phi{create_instruction(opcode, Format::PSEUDO, preds.size(), 1)}; - rename = {ctx.program->allocateId(), pair.first.regClass()}; + rename = ctx.program->allocateTmp(pair.first.regClass()); for (unsigned i = 0; i < phi->operands.size(); i++) { Temp tmp; if (ctx.renames[preds[i]].find(pair.first) != ctx.renames[preds[i]].end()) @@ -1107,7 +1107,7 @@ void process_block(spill_ctx& ctx, unsigned block_idx, Block* block, continue; } /* the Operand is spilled: add it to reloads */ - Temp new_tmp = {ctx.program->allocateId(), op.regClass()}; + Temp new_tmp = ctx.program->allocateTmp(op.regClass()); ctx.renames[block_idx][op.getTemp()] = new_tmp; reloads[new_tmp] = std::make_pair(op.getTemp(), current_spills[op.getTemp()]); current_spills.erase(op.getTemp()); @@ -1608,7 +1608,7 @@ void assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr) { /* check if the linear vgpr already exists */ if (vgpr_spill_temps[spill_slot / ctx.wave_size] == Temp()) { - Temp linear_vgpr = {ctx.program->allocateId(), v1.as_linear()}; + Temp linear_vgpr = ctx.program->allocateTmp(v1.as_linear()); vgpr_spill_temps[spill_slot / ctx.wave_size] = linear_vgpr; aco_ptr create{create_instruction(aco_opcode::p_start_linear_vgpr, Format::PSEUDO, 0, 1)}; create->definitions[0] = Definition(linear_vgpr); @@ -1677,7 +1677,7 @@ void assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr) { /* check if the linear vgpr already exists */ if (vgpr_spill_temps[spill_slot / ctx.wave_size] == Temp()) { - Temp linear_vgpr = {ctx.program->allocateId(), v1.as_linear()}; + Temp linear_vgpr = ctx.program->allocateTmp(v1.as_linear()); vgpr_spill_temps[spill_slot / ctx.wave_size] = linear_vgpr; aco_ptr create{create_instruction(aco_opcode::p_start_linear_vgpr, Format::PSEUDO, 0, 1)}; create->definitions[0] = Definition(linear_vgpr);