From: plind44@gmail.com Date: Wed, 5 Feb 2014 22:28:46 +0000 (+0000) Subject: MIPS: Fix crashes after profile entry hook calls. X-Git-Tag: upstream/4.7.83~10858 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ec0c4b453f1a482a2067a0d479a34112d971b51a;p=platform%2Fupstream%2Fv8.git MIPS: Fix crashes after profile entry hook calls. The call to C++ function has to be done through t9 register for the position independent code. The crashes occur only for shared library build. TEST=cctest/test-api/SetFunctionEntryHook BUG= R=plind44@gmail.com Review URL: https://codereview.chromium.org/132113009 Patch from Dusan Milosavljevic . git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19121 ce2b1a6d-e550-0410-aec6-3dcde31c8c00 --- diff --git a/src/mips/code-stubs-mips.cc b/src/mips/code-stubs-mips.cc index 05ddf87..e38f181 100644 --- a/src/mips/code-stubs-mips.cc +++ b/src/mips/code-stubs-mips.cc @@ -5267,11 +5267,11 @@ void ProfileEntryHookStub::Generate(MacroAssembler* masm) { ASSERT(IsPowerOf2(frame_alignment)); __ And(sp, sp, Operand(-frame_alignment)); } - + __ Subu(sp, sp, kCArgsSlotsSize); #if defined(V8_HOST_ARCH_MIPS) int32_t entry_hook = reinterpret_cast(masm->isolate()->function_entry_hook()); - __ li(at, Operand(entry_hook)); + __ li(t9, Operand(entry_hook)); #else // Under the simulator we need to indirect the entry hook through a // trampoline function at a known address. @@ -5279,15 +5279,18 @@ void ProfileEntryHookStub::Generate(MacroAssembler* masm) { __ li(a2, Operand(ExternalReference::isolate_address(masm->isolate()))); ApiFunction dispatcher(FUNCTION_ADDR(EntryHookTrampoline)); - __ li(at, Operand(ExternalReference(&dispatcher, + __ li(t9, Operand(ExternalReference(&dispatcher, ExternalReference::BUILTIN_CALL, masm->isolate()))); #endif - __ Call(at); + // Call C function through t9 to conform ABI for PIC. + __ Call(t9); // Restore the stack pointer if needed. if (frame_alignment > kPointerSize) { __ mov(sp, s5); + } else { + __ Addu(sp, sp, kCArgsSlotsSize); } // Also pop ra to get Ret(0).