From: rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Wed, 8 Dec 2010 16:38:10 +0000 (+0000)
Subject: 2010-12-08  Richard Earnshaw  <rearnsha@arm.com>
X-Git-Tag: upstream/4.9.2~24304
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ec0106bcc2fc80f815417a6002acae7bf9036ba9;p=platform%2Fupstream%2Flinaro-gcc.git

2010-12-08  Richard Earnshaw  <rearnsha@arm.com>

	PR target/46631
	* arm.c (thumb2_reorg): Also try to reduce <commutative_op> Rd, Rn, Rd
	into a 16-bit instruction.

2010-12-08  Wei Guozhi  <carrot@google.com>

	PR target/46631
	* gcc.target/arm/pr46631: New testcase.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@167595 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6428570..7f039b1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2010-12-08  Richard Earnshaw  <rearnsha@arm.com>
+
+	PR target/46631
+	* arm.c (thumb2_reorg): Also try to reduce <commutative_op> Rd, Rn, Rd
+	into a 16-bit instruction.
+
 2010-12-08  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	PR middle-end/42694
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 88c43e3..9d2c6dd 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -12183,6 +12183,7 @@ thumb2_reorg (void)
   FOR_EACH_BB (bb)
     {
       rtx insn;
+
       COPY_REG_SET (&live, DF_LR_OUT (bb));
       df_simulate_initialize_backwards (bb, &live);
       FOR_BB_INSNS_REVERSE (bb, insn)
@@ -12200,21 +12201,43 @@ thumb2_reorg (void)
 		  rtx dst = XEXP (pat, 0);
 		  rtx src = XEXP (pat, 1);
 		  rtx op0 = XEXP (src, 0);
+		  rtx op1 = (GET_RTX_CLASS (GET_CODE (src)) == RTX_COMM_ARITH
+			     ? XEXP (src, 1) : NULL);
+
 		  if (rtx_equal_p (dst, op0)
 		      || GET_CODE (src) == PLUS || GET_CODE (src) == MINUS)
 		    {
 		      rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM);
 		      rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg);
 		      rtvec vec = gen_rtvec (2, pat, clobber);
+
+		      PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
+		      INSN_CODE (insn) = -1;
+		    }
+		  /* We can also handle a commutative operation where the
+		     second operand matches the destination.  */
+		  else if (op1 && rtx_equal_p (dst, op1))
+		    {
+		      rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM);
+		      rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg);
+		      rtvec vec;
+
+		      src = copy_rtx (src);
+		      XEXP (src, 0) = op1;
+		      XEXP (src, 1) = op0;
+		      pat = gen_rtx_SET (VOIDmode, dst, src);
+		      vec = gen_rtvec (2, pat, clobber);
 		      PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
 		      INSN_CODE (insn) = -1;
 		    }
 		}
 	    }
+
 	  if (NONDEBUG_INSN_P (insn))
 	    df_simulate_one_insn_backwards (bb, insn, &live);
 	}
     }
+
   CLEAR_REG_SET (&live);
 }
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7a7f3be..313af80 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2010-12-08  Wei Guozhi  <carrot@google.com>
+
+	PR target/46631
+	* gcc.target/arm/pr46631: New testcase.
+
 2010-12-08  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	PR middle-end/42694
diff --git a/gcc/testsuite/gcc.target/arm/pr46631.c b/gcc/testsuite/gcc.target/arm/pr46631.c
new file mode 100644
index 0000000..6f6dc4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr46631.c
@@ -0,0 +1,16 @@
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "ands" } } */
+
+struct S {
+      int bi_buf;
+      int bi_valid;
+};
+
+int tz (struct S* p, int bits, int value)
+{
+     if (p == 0) return 1;
+      p->bi_valid = bits;
+      p->bi_buf = value & ((1 << bits) - 1);
+      return 0;
+}