From: Alyssa Rosenzweig <alyssa@collabora.com>
Date: Tue, 7 Dec 2021 23:55:57 +0000 (-0500)
Subject: pan/bi: Add LD_VAR_BUF_IMM.f16/f32 instructions
X-Git-Tag: upstream/22.3.5~12107
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=eba9ef4c2529fc88ed5bdf88a5b22d6f13e73faa;p=platform%2Fupstream%2Fmesa.git

pan/bi: Add LD_VAR_BUF_IMM.f16/f32 instructions

For use on Valhall with memory-allocated IDVS jobs.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
---

diff --git a/src/panfrost/bifrost/ISA.xml b/src/panfrost/bifrost/ISA.xml
index fb26ab6..20018ba 100644
--- a/src/panfrost/bifrost/ISA.xml
+++ b/src/panfrost/bifrost/ISA.xml
@@ -8505,4 +8505,64 @@
     <mod name="neg2" size="1" opt="neg"/>
   </ins>
 
+  <ins name="+LD_VAR_BUF_IMM.f32" staging="w=format" message="varying" pseudo="true">
+    <src start="0"/>
+    <immediate name="index" start="3" size="5"/>
+    <mod name="vecsize" start="8" size="2">
+      <opt>none</opt>
+      <opt>v2</opt>
+      <opt>v3</opt>
+      <opt>v4</opt>
+    </mod>
+    <mod name="update" size="2">
+      <opt>store</opt>
+      <opt>retrieve</opt>
+      <opt>conditional</opt>
+      <opt>clobber</opt>
+    </mod>
+    <mod name="register_format" size="2">
+      <opt>f32</opt>
+      <opt>f16</opt>
+      <opt>u32</opt>
+      <opt>u16</opt>
+    </mod>
+    <mod name="sample" size="3">
+      <opt>center</opt>
+      <opt>centroid</opt>
+      <opt>sample</opt>
+      <opt>explicit</opt>
+      <opt>none</opt>
+    </mod>
+  </ins>
+
+  <ins name="+LD_VAR_BUF_IMM.f16" staging="w=format" message="varying" pseudo="true">
+    <src start="0"/>
+    <immediate name="index" start="3" size="5"/>
+    <mod name="vecsize" start="8" size="2">
+      <opt>none</opt>
+      <opt>v2</opt>
+      <opt>v3</opt>
+      <opt>v4</opt>
+    </mod>
+    <mod name="update" size="2">
+      <opt>store</opt>
+      <opt>retrieve</opt>
+      <opt>conditional</opt>
+      <opt>clobber</opt>
+    </mod>
+    <mod name="register_format" size="2">
+      <opt>f32</opt>
+      <opt>f16</opt>
+      <opt>u32</opt>
+      <opt>u16</opt>
+    </mod>
+    <mod name="sample" size="3">
+      <opt>center</opt>
+      <opt>centroid</opt>
+      <opt>sample</opt>
+      <opt>explicit</opt>
+      <opt>none</opt>
+    </mod>
+  </ins>
+
 </bifrost>