From: Peter Maydell Date: Fri, 8 Jan 2021 19:51:57 +0000 (+0000) Subject: target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns X-Git-Tag: upstream/5.2.0~138 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e9d6c6f274dad90638177219366a67a7b98ad459;p=platform%2Fupstream%2Fqemu.git target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns Git-commit: e4d51ac6921dc861bfb3d20e4c7dcf345840a9da In commit cd8be50e58f63413c0 we converted the A32 coprocessor insns to decodetree. This accidentally broke XScale/iWMMXt insns, because it moved the handling of "cp insns which are handled by looking up the cp register in the hashtable" from after the call to the legacy disas_xscale_insn() decode to before it, with the result that all XScale/iWMMXt insns now UNDEF. Update valid_cp() so that it knows that on XScale cp 0 and 1 are not standard coprocessor instructions; this will cause the decodetree trans_ functions to ignore them, so that execution will correctly get through to the legacy decode again. Cc: qemu-stable@nongnu.org Reported-by: Guenter Roeck Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Guenter Roeck Message-id: 20210108195157.32067-1-peter.maydell@linaro.org Signed-off-by: Bruce Rogers --- diff --git a/target/arm/translate.c b/target/arm/translate.c index 6d04ca3..8089a4f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5275,7 +5275,14 @@ static bool valid_cp(DisasContext *s, int cp) * only cp14 and cp15 are valid, and other values aren't considered * to be in the coprocessor-instruction space at all. v8M still * permits coprocessors 0..7. + * For XScale, we must not decode the XScale cp0, cp1 space as + * a standard coprocessor insn, because we want to fall through to + * the legacy disas_xscale_insn() decoder after decodetree is done. */ + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_V8) && !arm_dc_feature(s, ARM_FEATURE_M)) { return cp >= 14;