From: Chen-Yu Tsai Date: Thu, 15 Sep 2016 15:14:00 +0000 (+0800) Subject: drm/sun4i: dotclock: Fix clock rate read back calcation X-Git-Tag: v4.9.8~1110^2~18^2~6 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e996e2089f25b84149ae82b5ddf37a263a7fcc71;p=platform%2Fkernel%2Flinux-rpi3.git drm/sun4i: dotclock: Fix clock rate read back calcation When reading back the divider set in the register, we mask off the bits that aren't part of the divider. Unfortunately the mask used here was not converted from the field width. Fix this by converting the field width to a proper bit mask. Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c index 4332da4..1b6c225 100644 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c @@ -62,7 +62,7 @@ static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw, regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); val >>= SUN4I_TCON0_DCLK_DIV_SHIFT; - val &= SUN4I_TCON0_DCLK_DIV_WIDTH; + val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1; if (!val) val = 1;