From: Jeff Law <law@redhat.com>
Date: Thu, 29 Aug 1996 20:08:37 +0000 (+0000)
Subject:         * simops.c: Add multiply & divide support.  Abort for system
X-Git-Tag: gdb-4_18~7827
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e98e3b2c5a56e32cd0f0a83e7ee7977673ddd142;p=external%2Fbinutils.git

    * simops.c: Add multiply & divide support.  Abort for system
        instructions.
---

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index bfb9946..546b2bd 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,5 +1,8 @@
 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 
+	* simops.c: Add multiply & divide support.  Abort for system
+	instructions.
+
 	* simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 	and subr.  No condition codes yet.
 
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index f286e70..13d77ae 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -43,11 +43,6 @@ OP_581 ()
 }
 
 void
-OP_40 ()
-{
-}
-
-void
 OP_582 ()
 {
 }
@@ -108,11 +103,6 @@ OP_400 ()
 }
 
 void
-OP_2E0 ()
-{
-}
-
-void
 OP_160 ()
 {
 }
@@ -137,20 +127,6 @@ OP_660 ()
 {
 }
 
-void
-OP_E0 ()
-{
-}
-
-void
-OP_16087E0 ()
-{
-}
-
-void
-OP_16007E0 ()
-{
-}
 
 /* add reg, reg
 
@@ -205,23 +181,59 @@ OP_180 ()
   State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]];
 }
 
+/* mulh reg1, reg2
+
+   XXX condition codes */
 void
-OP_8007E0 ()
+OP_E0 ()
 {
+  State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
+		       * (State.regs[OP[2]] & 0xffff));
 }
 
+/* mulh sign_extend(imm5), reg2
+
+   Condition codes */
 void
-OP_C007E0 ()
+OP_2E0 ()
 {
+  int value = OP[0];
+ 
+  value = (value << 27) >> 27;
+
+  State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
 }
 
+/* mulhi imm16, reg1, reg2
+
+   XXX condition codes */
 void
-OP_12007E0 ()
+OP_6E0 ()
+{
+  int value = OP[0];
+ 
+  value = value & 0xffff;
+
+  State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
+}
+
+/* divh reg1, reg2
+
+   XXX condition codes.
+   XXX Is this signed or unsigned?  */
+void
+OP_40 ()
 {
+  State.regs[OP[1]] /= (State.regs[OP[1]] & 0xffff);
 }
 
 void
-OP_4007E0 ()
+OP_8007E0 ()
+{
+}
+
+void
+OP_C007E0 ()
 {
 }
 
@@ -326,11 +338,6 @@ OP_260 ()
 }
 
 void
-OP_6E0 ()
-{
-}
-
-void
 OP_740 ()
 {
 }
@@ -340,11 +347,6 @@ OP_80 ()
 {
 }
 
-void
-OP_14007E0 ()
-{
-}
-
 /* not reg1, reg2
 
    XXX condition codes */
@@ -370,21 +372,11 @@ OP_2C0 ()
 }
 
 void
-OP_10007E0 ()
-{
-}
-
-void
 OP_47C0 ()
 {
 }
 
 void
-OP_2007E0 ()
-{
-}
-
-void
 OP_7E0 ()
 {
 }
@@ -474,3 +466,53 @@ void
 OP_501 ()
 {
 }
+
+/* di, not supported */
+void
+OP_16007E0 ()
+{
+  abort ();
+}
+
+/* ei, not supported */
+void
+OP_16087E0 ()
+{
+  abort ();
+}
+
+/* halt, not supported */
+void
+OP_12007E0 ()
+{
+  abort ();
+}
+
+/* reti, not supported */
+void
+OP_14007E0 ()
+{
+  abort ();
+}
+
+/* trap, not supportd */
+void
+OP_10007E0 ()
+{
+  abort ();
+}
+
+/* ldsr, not supported */
+void
+OP_2007E0 ()
+{
+  abort ();
+}
+
+/* stsr, not supported */
+void
+OP_4007E0 ()
+{
+  abort ();
+}
+