From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 5 Oct 2020 13:43:44 +0000 (+0200)
Subject: arm64: zynqmp: Enable FPGA loading from SPL
X-Git-Tag: v2021.10~455^2~49
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e9284066958e906118b3fd71d7e81e9916b2c58a;p=platform%2Fkernel%2Fu-boot.git

arm64: zynqmp: Enable FPGA loading from SPL

fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 264b662..5b4fe53 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -19,6 +19,7 @@ CONFIG_USE_PREBOOT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_FPGA=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y