From: Zhigang Gong <zhigang.gong@intel.com>
Date: Mon, 19 May 2014 09:51:14 +0000 (+0800)
Subject: GBE: fix one post register allocation instruction scheduling bug.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e91d0d608a2843942937533b3afb7faee53af591;p=contrib%2Fbeignet.git

GBE: fix one post register allocation instruction scheduling bug.

The instuction has modFlag 1 indicating it will modify the flag.

Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
---

diff --git a/backend/src/backend/gen_insn_scheduling.cpp b/backend/src/backend/gen_insn_scheduling.cpp
index a711f45..c3c4728 100644
--- a/backend/src/backend/gen_insn_scheduling.cpp
+++ b/backend/src/backend/gen_insn_scheduling.cpp
@@ -338,7 +338,7 @@ namespace gbe
     }
 
     // Track writes in predicates
-    if (insn.opcode == SEL_OP_CMP || insn.opcode == SEL_OP_I64CMP) {
+    if (insn.opcode == SEL_OP_CMP || insn.opcode == SEL_OP_I64CMP || insn.state.modFlag) {
       const uint32_t index = this->getIndex(getFlag(insn));
       this->nodes[index] = node;
     }
@@ -460,7 +460,7 @@ namespace gbe
         tracker.addDependency(node, insn.dst(dstID));
 
       // write-after-write for predicate
-      if (insn.opcode == SEL_OP_CMP || insn.opcode == SEL_OP_I64CMP)
+      if (insn.opcode == SEL_OP_CMP || insn.opcode == SEL_OP_I64CMP || insn.state.modFlag)
         tracker.addDependency(node, getFlag(insn));
 
       // write-after-write for accumulators
@@ -530,7 +530,7 @@ namespace gbe
     // Make labels and branches non-schedulable (i.e. they act as barriers)
     for (int32_t insnID = 0; insnID < insnNum; ++insnID) {
       ScheduleDAGNode *node = tracker.insnNodes[insnID];
-      if (node->insn.isBranch() || node->insn.isLabel() || node->insn.opcode == SEL_OP_EOT)
+      if (node->insn.isBranch() || node->insn.isLabel() || node->insn.opcode == SEL_OP_EOT || node->insn.opcode == SEL_OP_IF)
         tracker.makeBarrier(insnID, insnNum);
     }