From: Andre Przywara Date: Mon, 7 Sep 2020 12:18:27 +0000 (+0100) Subject: ARM: dts: nspire: Fix SP804 users X-Git-Tag: v5.15~2574^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e916bfacf558ee835c480d2c2dad9d144baf9e1c;p=platform%2Fkernel%2Flinux-starfive.git ARM: dts: nspire: Fix SP804 users Even though the SP804 binding allows to specify only one clock, the primecell driver requires a named clock to activate the bus clock. Specify the one clock three times and provide some clock-names, to make the DT match the SP804 and primecell binding. Link: https://lore.kernel.org/r/20200907121831.242281-3-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Olof Johansson --- diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index d9a0fd7..90e033d 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -145,15 +145,19 @@ timer0: timer@900C0000 { reg = <0x900C0000 0x1000>; - - clocks = <&timer_clk>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; }; timer1: timer@900D0000 { reg = <0x900D0000 0x1000>; interrupts = <19>; - - clocks = <&timer_clk>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; }; watchdog: watchdog@90060000 {