From: Radhey Shyam Pandey Date: Mon, 7 Aug 2023 05:51:41 +0000 (+0530) Subject: dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property X-Git-Tag: v6.6.7~1989^2~19 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e8cfa385054c6aa7ae8dd743d8ea980039a0fc0b;p=platform%2Fkernel%2Flinux-starfive.git dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt timeout value and causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs. This property is useful when AXI DMA is connected to the streaming IP i.e axiethernet where inter packet latency is critical while still taking the benefit of interrupt coalescing. Signed-off-by: Radhey Shyam Pandey Acked-by: Rob Herring Link: https://lore.kernel.org/r/1691387509-2113129-3-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul --- diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index fea5b09..590d194 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -52,7 +52,9 @@ Optional properties for AXI DMA and MCDMA: Optional properties for AXI DMA: - xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. - +- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from + 0-255. Setting this value to zero disables the delay timer interrupt. + 1 timeout interval = 125 * clock period of SG clock. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values: