From: Zenghui Yu Date: Thu, 6 Feb 2020 07:57:06 +0000 (+0800) Subject: irqchip/gic-v4.1: Fix programming of GICR_VPROPBASER_4_1_SIZE X-Git-Tag: v5.15~4313^2^2~6 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e88bd316e5971fe78884ad1f466b9fc576575e5f;p=platform%2Fkernel%2Flinux-starfive.git irqchip/gic-v4.1: Fix programming of GICR_VPROPBASER_4_1_SIZE The Size field of GICv4.1 VPROPBASER register indicates number of pages minus one and together Page_Size and Size control the vPEID width. Let's respect this requirement of the architecture. Signed-off-by: Zenghui Yu Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20200206075711.1275-2-yuzenghui@huawei.com --- diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e5a25d9..992bc72 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -2531,7 +2531,7 @@ static int allocate_vpe_l1_table(void) npg = 1; } - val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg); + val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1); /* Right, that's the number of CPU pages we need for L1 */ np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);