From: Alejandro Piñeiro <apinheiro@igalia.com>
Date: Fri, 22 Oct 2021 09:40:49 +0000 (+0200)
Subject: v3d: setup render pass color clears for any format bpp in v71
X-Git-Tag: upstream/23.3.3~824
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e743d41756101cce7cda469895f76d60de8506a7;p=platform%2Fupstream%2Fmesa.git

v3d: setup render pass color clears for any format bpp in v71

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
---

diff --git a/src/gallium/drivers/v3d/v3dx_rcl.c b/src/gallium/drivers/v3d/v3dx_rcl.c
index f59e055..8bac973 100644
--- a/src/gallium/drivers/v3d/v3dx_rcl.c
+++ b/src/gallium/drivers/v3d/v3dx_rcl.c
@@ -979,6 +979,24 @@ v3dX(emit_rcl)(struct v3d_job *job)
 
                         base_addr += (job->tile_height * rt.stride) / 8;
                 }
+
+                if (surf->internal_bpp >= V3D_INTERNAL_BPP_64) {
+                        cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_RENDER_TARGET_PART2, rt) {
+                                rt.clear_color_mid_bits = /* 40 bits (32 + 8)  */
+                                        ((uint64_t) job->clear_color[i][1]) |
+                                        (((uint64_t) (job->clear_color[i][2] & 0xff)) << 32);
+                                rt.render_target_number = i;
+                        }
+                }
+
+                if (surf->internal_bpp >= V3D_INTERNAL_BPP_128) {
+                        cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_RENDER_TARGET_PART3, rt) {
+                                rt.clear_color_top_bits = /* 56 bits (24 + 32) */
+                                        (((uint64_t) (job->clear_color[i][2] & 0xffffff00)) >> 8) |
+                                        (((uint64_t) (job->clear_color[i][3])) << 24);
+                                rt.render_target_number = i;
+                        }
+                }
 #endif
         }