From: Nicolai Haehnle <nhaehnle@gmail.com>
Date: Thu, 21 Jun 2018 13:36:33 +0000 (+0000)
Subject: AMDGPU: Use generic tables instead of SearchableTable
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e741d7e0fd90c5b1599fd1539c7ca2728adc76dd;p=platform%2Fupstream%2Fllvm.git

AMDGPU: Use generic tables instead of SearchableTable

Summary:

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D48014

Change-Id: Ibb43f90d955275571aff17d0c3ecfb5e5b299641
llvm-svn: 335226
---

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
index 438ea0e..81beb1a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
@@ -28,10 +28,10 @@ using namespace llvm;
 
 namespace llvm {
 namespace AMDGPU {
-#define GET_RSRCINTRINSIC_IMPL
+#define GET_RsrcIntrinsics_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 
-#define GET_D16IMAGEDIMINTRINSIC_IMPL
+#define GET_D16ImageDimIntrinsics_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 }
 }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
index a1ea3ff..057b674 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
@@ -61,13 +61,13 @@ struct RsrcIntrinsic {
   uint8_t RsrcArg;
   bool IsImage;
 };
-const RsrcIntrinsic *lookupRsrcIntrinsicByIntr(unsigned Intr);
+const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
 
 struct D16ImageDimIntrinsic {
   unsigned Intr;
   unsigned D16HelperIntr;
 };
-const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsicByIntr(unsigned Intr);
+const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
 
 } // end AMDGPU namespace
 } // End llvm namespace
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
index fce7499..bfe2018 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
@@ -13,15 +13,20 @@ include "llvm/TableGen/SearchableTable.td"
 // Resource intrinsics table.
 //===----------------------------------------------------------------------===//
 
-class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> : SearchableTable {
-  let SearchableFields = ["Intr"];
-  let EnumNameField = ?;
-
+class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> {
   Intrinsic Intr = !cast<Intrinsic>(intr);
   bits<8> RsrcArg = intr.RsrcArg;
   bit IsImage = intr.IsImage;
 }
 
+def RsrcIntrinsics : GenericTable {
+  let FilterClass = "RsrcIntrinsic";
+  let Fields = ["Intr", "RsrcArg", "IsImage"];
+
+  let PrimaryKey = ["Intr"];
+  let PrimaryKeyName = "lookupRsrcIntrinsic";
+}
+
 foreach intr = !listconcat(AMDGPUBufferIntrinsics,
                            AMDGPUImageIntrinsics,
                            AMDGPUImageDimIntrinsics,
@@ -31,13 +36,18 @@ foreach intr = !listconcat(AMDGPUBufferIntrinsics,
   def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
 }
 
-class SourceOfDivergence<Intrinsic intr> : SearchableTable {
-  let SearchableFields = ["Intr"];
-  let EnumNameField = ?;
-
+class SourceOfDivergence<Intrinsic intr> {
   Intrinsic Intr = intr;
 }
 
+def SourcesOfDivergence : GenericTable {
+  let FilterClass = "SourceOfDivergence";
+  let Fields = ["Intr"];
+
+  let PrimaryKey = ["Intr"];
+  let PrimaryKeyName = "lookupSourceOfDivergence";
+}
+
 def : SourceOfDivergence<int_amdgcn_workitem_id_x>;
 def : SourceOfDivergence<int_amdgcn_workitem_id_y>;
 def : SourceOfDivergence<int_amdgcn_workitem_id_z>;
@@ -84,15 +94,20 @@ def : SourceOfDivergence<int_amdgcn_ds_swizzle>;
 foreach intr = AMDGPUImageDimAtomicIntrinsics in
 def : SourceOfDivergence<intr>;
 
-class D16ImageDimIntrinsic<AMDGPUImageDimIntrinsic intr> : SearchableTable {
-  let SearchableFields = ["Intr"];
-  let EnumNameField = ?;
-
+class D16ImageDimIntrinsic<AMDGPUImageDimIntrinsic intr> {
   Intrinsic Intr = intr;
   code D16HelperIntr =
       !cast<code>("AMDGPUIntrinsic::SI_image_d16helper_" # intr.P.OpMod # intr.P.Dim.Name);
 }
 
+def D16ImageDimIntrinsics : GenericTable {
+  let FilterClass = "D16ImageDimIntrinsic";
+  let Fields = ["Intr", "D16HelperIntr"];
+
+  let PrimaryKey = ["Intr"];
+  let PrimaryKeyName = "lookupD16ImageDimIntrinsic";
+}
+
 foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
                            AMDGPUImageDimGatherIntrinsics) in {
   def : D16ImageDimIntrinsic<intr>;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 10005eb..b0c2197 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -649,7 +649,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
                                           MachineFunction &MF,
                                           unsigned IntrID) const {
   if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
-          AMDGPU::lookupRsrcIntrinsicByIntr(IntrID)) {
+          AMDGPU::lookupRsrcIntrinsic(IntrID)) {
     AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
                                                   (Intrinsic::ID)IntrID);
     if (Attr.hasFnAttribute(Attribute::ReadNone))
@@ -5138,7 +5138,7 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
         Op.getValueType().isVector() &&
         Op.getValueType().getScalarSizeInBits() == 16) {
       if (const AMDGPU::D16ImageDimIntrinsic *D16ImageDimIntr =
-            AMDGPU::lookupD16ImageDimIntrinsicByIntr(IntrID)) {
+            AMDGPU::lookupD16ImageDimIntrinsic(IntrID)) {
         return adjustLoadValueType(D16ImageDimIntr->D16HelperIntr,
                                    cast<MemSDNode>(Op), DAG, true);
       }
@@ -5393,7 +5393,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
   }
   default: {
     const AMDGPU::D16ImageDimIntrinsic *D16ImageDimIntr =
-        AMDGPU::lookupD16ImageDimIntrinsicByIntr(IntrinsicID);
+        AMDGPU::lookupD16ImageDimIntrinsic(IntrinsicID);
     if (D16ImageDimIntr) {
       SDValue VData = Op.getOperand(2);
       EVT StoreVT = VData.getValueType();
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index da9b98b..4d98768 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -951,15 +951,15 @@ namespace {
 struct SourceOfDivergence {
   unsigned Intr;
 };
-const SourceOfDivergence *lookupSourceOfDivergenceByIntr(unsigned Intr);
+const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
 
-#define GET_SOURCEOFDIVERGENCE_IMPL
+#define GET_SourcesOfDivergence_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 
 } // end anonymous namespace
 
 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
-  return lookupSourceOfDivergenceByIntr(IntrID);
+  return lookupSourceOfDivergence(IntrID);
 }
 } // namespace AMDGPU
 } // namespace llvm