From: Alexei Starovoitov Date: Sun, 20 Nov 2016 02:25:00 +0000 (+0000) Subject: [bpf] add BPF disassembler X-Git-Tag: llvmorg-4.0.0-rc1~4064 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e6ddac0def7c2e9c1c250e2eee06cf02d0cea65d;p=platform%2Fupstream%2Fllvm.git [bpf] add BPF disassembler add BPF disassembler, so tools like llvm-objdump can be used: $ llvm-objdump -d -no-show-raw-insn ./sockex1_kern.o ./sockex1_kern.o: file format ELF64-BPF Disassembly of section socket1: bpf_prog1: 0: r6 = r1 8: r0 = *(u8 *)skb[23] 10: *(u32 *)(r10 - 4) = r0 18: r1 = *(u32 *)(r6 + 4) 20: if r1 != 4 goto 8 28: r2 = r10 30: r2 += -4 ld_imm64 (the only 16-byte insn) and special ld_abs/ld_ind instructions had to be treated in a special way. The decoders for the rest of the insns are automatically generated. Add tests to cover new functionality. Signed-off-by: Alexei Starovoitov llvm-svn: 287477 --- diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td index 1f766bf..a7910de 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.td +++ b/llvm/lib/Target/BPF/BPFInstrInfo.td @@ -61,6 +61,7 @@ def FIri : ComplexPattern; def MEMri : Operand { let PrintMethod = "printMemOperand"; let EncoderMethod = "getMemoryOpValue"; + let DecoderMethod = "decodeMemoryOpValue"; let MIOperandInfo = (ops GPR, i16imm); } @@ -267,6 +268,13 @@ def FI_ri [(set i64:$dst, FIri:$addr)]> { // This is a tentative instruction, and will be replaced // with MOV_rr and ADD_ri in PEI phase + let Inst{63-61} = 0; + let Inst{60-59} = 3; + let Inst{51-48} = 0; + let Inst{55-52} = 2; + let Inst{47-32} = 0; + let Inst{31-0} = 0; + let BPFClass = 0; } @@ -476,13 +484,13 @@ class XADD SizeOp, string OpcodeStr, PatFrag OpNode> [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> { bits<3> mode; bits<2> size; - bits<4> src; + bits<4> dst; bits<20> addr; let Inst{63-61} = mode; let Inst{60-59} = size; let Inst{51-48} = addr{19-16}; // base reg - let Inst{55-52} = src; + let Inst{55-52} = dst; let Inst{47-32} = addr{15-0}; // offset let mode = 6; // BPF_XADD diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt index 3eac6e9..e2654b0 100644 --- a/llvm/lib/Target/BPF/CMakeLists.txt +++ b/llvm/lib/Target/BPF/CMakeLists.txt @@ -2,6 +2,7 @@ set(LLVM_TARGET_DEFINITIONS BPF.td) tablegen(LLVM BPFGenRegisterInfo.inc -gen-register-info) tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info) +tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM BPFGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel) @@ -22,6 +23,7 @@ add_llvm_target(BPFCodeGen BPFTargetMachine.cpp ) +add_subdirectory(Disassembler) add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp new file mode 100644 index 0000000..b0037fb --- /dev/null +++ b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp @@ -0,0 +1,154 @@ +//===- BPFDisassembler.cpp - Disassembler for BPF ---------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is part of the BPF Disassembler. +// +//===----------------------------------------------------------------------===// + +#include "BPF.h" +#include "BPFRegisterInfo.h" +#include "BPFSubtarget.h" +#include "MCTargetDesc/BPFMCTargetDesc.h" + +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +#define DEBUG_TYPE "bpf-disassembler" + +typedef MCDisassembler::DecodeStatus DecodeStatus; + +namespace { + +/// A disassembler class for BPF. +class BPFDisassembler : public MCDisassembler { +public: + BPFDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) + : MCDisassembler(STI, Ctx) {} + virtual ~BPFDisassembler() {} + + DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef Bytes, uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const override; +}; +} + +static MCDisassembler *createBPFDisassembler(const Target &T, + const MCSubtargetInfo &STI, + MCContext &Ctx) { + return new BPFDisassembler(STI, Ctx); +} + + +extern "C" void LLVMInitializeBPFDisassembler() { + // Register the disassembler. + TargetRegistry::RegisterMCDisassembler(getTheBPFTarget(), + createBPFDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheBPFleTarget(), + createBPFDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheBPFbeTarget(), + createBPFDisassembler); +} + +static const unsigned GPRDecoderTable[] = { + BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, + BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11}; + +static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const void * /*Decoder*/) { + if (RegNo > 11) + return MCDisassembler::Fail; + + unsigned Reg = GPRDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + unsigned Register = (Insn >> 16) & 0xf; + Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); + unsigned Offset = (Insn & 0xffff); + Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); + + return MCDisassembler::Success; +} + +#include "BPFGenDisassemblerTables.inc" + +static DecodeStatus readInstruction64(ArrayRef Bytes, uint64_t Address, + uint64_t &Size, uint64_t &Insn) { + uint64_t Lo, Hi; + + if (Bytes.size() < 8) { + Size = 0; + return MCDisassembler::Fail; + } + + Size = 8; + Hi = (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 0) | (Bytes[3] << 8); + Lo = (Bytes[4] << 0) | (Bytes[5] << 8) | (Bytes[6] << 16) | (Bytes[7] << 24); + Insn = Make_64(Hi, Lo); + + return MCDisassembler::Success; +} + +DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef Bytes, + uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const { + uint64_t Insn; + DecodeStatus Result; + + Result = readInstruction64(Bytes, Address, Size, Insn); + if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; + + Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, + Address, this, STI); + if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; + + switch (Instr.getOpcode()) { + case BPF::LD_imm64: { + if (Bytes.size() < 16) { + Size = 0; + return MCDisassembler::Fail; + } + Size = 16; + uint64_t Hi = (Bytes[12] << 0) | (Bytes[13] << 8) | (Bytes[14] << 16) | (Bytes[15] << 24); + auto& Op = Instr.getOperand(1); + Op.setImm(Make_64(Hi, Op.getImm())); + break; + } + case BPF::LD_ABS_B: + case BPF::LD_ABS_H: + case BPF::LD_ABS_W: + case BPF::LD_IND_B: + case BPF::LD_IND_H: + case BPF::LD_IND_W: { + auto Op = Instr.getOperand(0); + Instr.clear(); + Instr.addOperand(MCOperand::createReg(BPF::R6)); + Instr.addOperand(Op); + break; + } + } + + return Result; +} + +typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, + const void *Decoder); diff --git a/llvm/lib/Target/BPF/Disassembler/CMakeLists.txt b/llvm/lib/Target/BPF/Disassembler/CMakeLists.txt new file mode 100644 index 0000000..c6dd1b3 --- /dev/null +++ b/llvm/lib/Target/BPF/Disassembler/CMakeLists.txt @@ -0,0 +1,4 @@ +add_llvm_library(LLVMBPFDisassembler + BPFDisassembler.cpp +) + diff --git a/llvm/lib/Target/BPF/Disassembler/LLVMBuild.txt b/llvm/lib/Target/BPF/Disassembler/LLVMBuild.txt new file mode 100644 index 0000000..786074d --- /dev/null +++ b/llvm/lib/Target/BPF/Disassembler/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/BPF/Disassembler/LLVMBuild.txt --------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = BPFDisassembler +parent = BPF +required_libraries = MCDisassembler BPFInfo Support +add_to_library_groups = BPF diff --git a/llvm/lib/Target/BPF/LLVMBuild.txt b/llvm/lib/Target/BPF/LLVMBuild.txt index 66dbf86..171536d 100644 --- a/llvm/lib/Target/BPF/LLVMBuild.txt +++ b/llvm/lib/Target/BPF/LLVMBuild.txt @@ -16,13 +16,14 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = InstPrinter MCTargetDesc TargetInfo +subdirectories = InstPrinter Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup name = BPF parent = Target has_asmprinter = 1 +has_disassembler = 1 [component_1] type = Library diff --git a/llvm/test/CodeGen/BPF/atomics.ll b/llvm/test/CodeGen/BPF/atomics.ll index c24dd65..64c45aa 100644 --- a/llvm/test/CodeGen/BPF/atomics.ll +++ b/llvm/test/CodeGen/BPF/atomics.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding | FileCheck %s ; CHECK-LABEL: test_load_add_32 -; CHECK: lock *(u32 *) -; CHECK: encoding: [0xc3 +; CHECK: lock *(u32 *)(r1 + 0) += r2 +; CHECK: encoding: [0xc3,0x21 define void @test_load_add_32(i32* %p, i32 zeroext %v) { entry: atomicrmw add i32* %p, i32 %v seq_cst @@ -10,8 +10,8 @@ entry: } ; CHECK-LABEL: test_load_add_64 -; CHECK: lock *(u64 *) -; CHECK: encoding: [0xdb +; CHECK: lock *(u64 *)(r1 + 0) += r2 +; CHECK: encoding: [0xdb,0x21 define void @test_load_add_64(i64* %p, i64 zeroext %v) { entry: atomicrmw add i64* %p, i64 %v seq_cst diff --git a/llvm/test/CodeGen/BPF/objdump_atomics.ll b/llvm/test/CodeGen/BPF/objdump_atomics.ll new file mode 100644 index 0000000..fb59449 --- /dev/null +++ b/llvm/test/CodeGen/BPF/objdump_atomics.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s + +; CHECK-LABEL: test_load_add_32 +; CHECK: c3 21 +; CHECK: lock *(u32 *)(r1 + 0) += r2 +define void @test_load_add_32(i32* %p, i32 zeroext %v) { +entry: + atomicrmw add i32* %p, i32 %v seq_cst + ret void +} + +; CHECK-LABEL: test_load_add_64 +; CHECK: db 21 +; CHECK: lock *(u64 *)(r1 + 0) += r2 +define void @test_load_add_64(i64* %p, i64 zeroext %v) { +entry: + atomicrmw add i64* %p, i64 %v seq_cst + ret void +} diff --git a/llvm/test/CodeGen/BPF/objdump_intrinsics.ll b/llvm/test/CodeGen/BPF/objdump_intrinsics.ll new file mode 100644 index 0000000..ddb92b9 --- /dev/null +++ b/llvm/test/CodeGen/BPF/objdump_intrinsics.ll @@ -0,0 +1,88 @@ +; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s + +; Function Attrs: nounwind uwtable +define i32 @ld_b(i64 %foo, i64* nocapture %bar, i8* %ctx, i8* %ctx2) #0 { + %1 = tail call i64 @llvm.bpf.load.byte(i8* %ctx, i64 123) #2 + %2 = add i64 %1, %foo + %3 = load volatile i64, i64* %bar, align 8 + %4 = add i64 %2, %3 + %5 = tail call i64 @llvm.bpf.load.byte(i8* %ctx2, i64 %foo) #2 + %6 = add i64 %4, %5 + %7 = load volatile i64, i64* %bar, align 8 + %8 = add i64 %6, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +; CHECK-LABEL: ld_b: +; CHECK: r0 = *(u8 *)skb[123] +; CHECK: r0 = *(u8 *)skb[r +} + +declare i64 @llvm.bpf.load.byte(i8*, i64) #1 + +; Function Attrs: nounwind uwtable +define i32 @ld_h(i8* %ctx, i8* %ctx2, i32 %foo) #0 { + %1 = tail call i64 @llvm.bpf.load.half(i8* %ctx, i64 123) #2 + %2 = sext i32 %foo to i64 + %3 = tail call i64 @llvm.bpf.load.half(i8* %ctx2, i64 %2) #2 + %4 = add i64 %3, %1 + %5 = trunc i64 %4 to i32 + ret i32 %5 +; CHECK-LABEL: ld_h: +; CHECK: r0 = *(u16 *)skb[r +; CHECK: r0 = *(u16 *)skb[123] +} + +declare i64 @llvm.bpf.load.half(i8*, i64) #1 + +; Function Attrs: nounwind uwtable +define i32 @ld_w(i8* %ctx, i8* %ctx2, i32 %foo) #0 { + %1 = tail call i64 @llvm.bpf.load.word(i8* %ctx, i64 123) #2 + %2 = sext i32 %foo to i64 + %3 = tail call i64 @llvm.bpf.load.word(i8* %ctx2, i64 %2) #2 + %4 = add i64 %3, %1 + %5 = trunc i64 %4 to i32 + ret i32 %5 +; CHECK-LABEL: ld_w: +; CHECK: r0 = *(u32 *)skb[r +; CHECK: r0 = *(u32 *)skb[123] +} + +declare i64 @llvm.bpf.load.word(i8*, i64) #1 + +define i32 @ld_pseudo() #0 { +entry: + %call = tail call i64 @llvm.bpf.pseudo(i64 2, i64 3) + tail call void @bar(i64 %call, i32 4) #2 + ret i32 0 +; CHECK-LABEL: ld_pseudo: +; CHECK: ld_pseudo r1, 2, 3 +} + +declare void @bar(i64, i32) #1 + +declare i64 @llvm.bpf.pseudo(i64, i64) #2 + +define i32 @bswap(i64 %a, i64 %b, i64 %c) #0 { +entry: + %0 = tail call i64 @llvm.bswap.i64(i64 %a) + %conv = trunc i64 %b to i32 + %1 = tail call i32 @llvm.bswap.i32(i32 %conv) + %conv1 = zext i32 %1 to i64 + %add = add i64 %conv1, %0 + %conv2 = trunc i64 %c to i16 + %2 = tail call i16 @llvm.bswap.i16(i16 %conv2) + %conv3 = zext i16 %2 to i64 + %add4 = add i64 %add, %conv3 + %conv5 = trunc i64 %add4 to i32 + ret i32 %conv5 +; CHECK-LABEL: bswap: +; CHECK: bswap64 r1 +; CHECK: bswap32 r2 +; CHECK: r2 += r1 +; CHECK: bswap16 r3 +; CHECK: r2 += r3 +} + +declare i64 @llvm.bswap.i64(i64) #1 +declare i32 @llvm.bswap.i32(i32) #1 +declare i16 @llvm.bswap.i16(i16) #1 diff --git a/llvm/test/CodeGen/BPF/objdump_trivial.ll b/llvm/test/CodeGen/BPF/objdump_trivial.ll new file mode 100644 index 0000000..48fee21 --- /dev/null +++ b/llvm/test/CodeGen/BPF/objdump_trivial.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=bpfel -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s + +; CHECK: if r2 s> r1 goto +; CHECK: call +; CHECK: exit + +declare void @a() +declare void @b() + +define void @foo(i32 %a) { +%b = icmp sgt i32 %a, -1 +br i1 %b, label %x, label %y +x: +call void @a() +ret void +y: +call void @b() +ret void +}