From: Filip Gawin <filip.gawin@zoho.com>
Date: Mon, 16 Aug 2021 11:13:43 +0000 (+0200)
Subject: radeonsi: improve rounding of zmin
X-Git-Tag: upstream/22.3.5~19170
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e6d996f8ff2e365b96de3e521275764ada317249;p=platform%2Fupstream%2Fmesa.git

radeonsi: improve rounding of zmin

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12389>
---

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 7f236fe..48283c0 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -476,7 +476,7 @@ static uint32_t si_get_htile_clear_value(struct si_texture *tex, float depth)
    const uint32_t smem  = 0;
 
    /* Convert depthValue to 14-bit zmin/zmax uint values. */
-   const uint32_t zmin = (depth * max_z_value) + 0.5f;
+   const uint32_t zmin = lroundf(depth * max_z_value);
    const uint32_t zmax = zmin;
 
    if (tex->htile_stencil_disabled) {