From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 18 Feb 2015 02:10:37 +0000 (+0000)
Subject: R600/SI: Fix operand encoding for flat instructions
X-Git-Tag: llvmorg-3.7.0-rc1~11725
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e6c5241814c99f4e5ce7875de540536ab186d26a;p=platform%2Fupstream%2Fllvm.git

R600/SI: Fix operand encoding for flat instructions

llvm-svn: 229607
---

diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td
index 5e68cb2..5203792 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.td
+++ b/llvm/lib/Target/R600/SIInstrInfo.td
@@ -1915,12 +1915,13 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
 }
 
 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
-      FLAT <op, (outs regClass:$data),
+      FLAT <op, (outs regClass:$vdst),
                 (ins VReg_64:$addr),
-            asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
+            asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
   let glc = 0;
   let slc = 0;
   let tfe = 0;
+  let data = 0;
   let mayLoad = 1;
 }
 
@@ -1936,6 +1937,7 @@ class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
   let glc = 0;
   let slc = 0;
   let tfe = 0;
+  let vdst = 0;
 }
 
 class MIMG_Mask <string op, int channels> {