From: Maciej W. Rozycki <macro@imgtec.com>
Date: Sun, 24 Jan 2016 00:49:26 +0000 (+0000)
Subject: MIPS/BFD: Correct register index calculation in BZ16_REG
X-Git-Tag: gdb-7.11-release~169
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e67f83e590b8ce7a9912f665aa559cbc98c05de6;p=platform%2Fupstream%2Fbinutils.git

MIPS/BFD: Correct register index calculation in BZ16_REG

For the 3-bit register encodings of { 0, 1, 2, 3, 4, 5, 6, 7 } return
the 5-bit encodings of { 16, 17, 2, 3, 4, 5, 6, 7 } respectively rather
than { 24, 25, 2, 3, 4, 5, 6, 7 }.

	bfd/
	* elfxx-mips.c (BZ16_REG): Correct calculation.
---

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 9c813ba..2e4f3b3 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,7 @@
+2016-01-24  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* elfxx-mips.c (BZ16_REG): Correct calculation.
+
 2016-01-21  Nick Clifton  <nickc@redhat.com>
 
 	* elf32-arc.c (ADD_RELA): Fix compile time warning errors by
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 4ece819..176970a 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -13110,7 +13110,7 @@ static const struct opcode_descriptor bz_insns_16[] = {
 
 /* Switch between a 5-bit register index and its 3-bit shorthand.  */
 
-#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0x17) + 2)
+#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0xf) + 2)
 #define BZ16_REG_FIELD(r) \
   (((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 7)