From: Kyungmin Park <kyungmin.park@samsung.com>
Date: Wed, 17 Jun 2009 09:53:35 +0000 (+0900)
Subject: [OneNAND] Use correct configurations for s5pc100
X-Git-Tag: s5pc110_universal_support~177
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e6732a38e796e66534b80db95c0befa8daffad11;p=kernel%2Fu-boot.git

[OneNAND] Use correct configurations for s5pc100

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---

diff --git a/board/samsung/tickertape/onenand.c b/board/samsung/tickertape/onenand.c
index 473d5ba..235c4c7 100644
--- a/board/samsung/tickertape/onenand.c
+++ b/board/samsung/tickertape/onenand.c
@@ -23,26 +23,17 @@ void onenand_board_init(struct mtd_info *mtd)
         struct onenand_chip *this = mtd->priv;
         int value;
 
-//	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
-	this->base = (void *) 0xe7100000;
-
-//	s3c_onenand_init(mtd);
-
 	/* D0 Domain system 1 clock gating */
-#if 0
 	value = S5P_CLK_GATE_D00_REG;
 	value &= ~(1 << 2);		/* CFCON */
 	value |= (1 << 2);
 	S5P_CLK_GATE_D00_REG = value;
-#endif
 
-#if 0
 	/* D0 Domain memory clock gating */
 	value = S5P_CLK_GATE_D01_REG;
 	value &= ~(1 << 2);		/* CLK_ONENANDC */
 	value |= (1 << 2);
 	S5P_CLK_GATE_D01_REG = value;
-#endif
 
 	/* System Special clock gating */
 	value = S5P_CLK_GATE_SCLK0_REG;
@@ -65,18 +56,11 @@ void onenand_board_init(struct mtd_info *mtd)
 
 	MEM_RESET0_REG = ONENAND_MEM_RESET_COLD;
 
-#if 0
 	while (!(INT_ERR_STAT0_REG & RST_CMP))
 		continue;
-#endif
 
-#if 0
-	INT_ERR_ACK0_REG |= RST_CMP;
-	INT_ERR_ACK0_REG = INT_ERR_STAT0_REG;
+	INT_ERR_ACK0_REG = RST_CMP;
 
-	WATCHDOG_CNT_LOW_REG = 0xffff;
-	WATCHDOG_CNT_HI_REG = 0xffff;
-#endif
 	ACC_CLOCK0_REG = 0x3;
 
 	INT_ERR_MASK0_REG = 0x03ff;
@@ -86,28 +70,24 @@ void onenand_board_init(struct mtd_info *mtd)
 	value &= ~RDY_ACT;
 	INT_ERR_MASK0_REG = value;
 
-//	MULTI_PLANE_REG = 0;
-//	SYNC_WRITE_REG = 1;
 #if 0
-	/* MEM_CFG0_REG = 0xf0e0; */
-	MEM_CFG0_REG =
-#ifdef CONFIG_SYNC_MODE
-#error not yet supported...
+	MEM_CFG0_REG |=
 		ONENAND_SYS_CFG1_SYNC_READ |
-#endif
 		ONENAND_SYS_CFG1_BRL_4 |
 		ONENAND_SYS_CFG1_BL_16 |
 		ONENAND_SYS_CFG1_RDY |
 		ONENAND_SYS_CFG1_INT |
 		ONENAND_SYS_CFG1_IOBE
 		;
-#else
-	MEM_CFG0_REG |= ONENAND_SYS_CFG1_BRL_4;
-	MEM_CFG0_REG |= ONENAND_SYS_CFG1_BL_16;
+	MEM_CFG0_REG |= ONENAND_SYS_CFG1_RDY;
+	MEM_CFG0_REG |=	ONENAND_SYS_CFG1_INT; 
+	MEM_CFG0_REG |= ONENAND_SYS_CFG1_IOBE;
+#endif
 	MEM_CFG0_REG |= ONENAND_SYS_CFG1_VHF;
 	MEM_CFG0_REG |= ONENAND_SYS_CFG1_HF;
-//	MEM_CFG0_REG |= ONENAND_SYS_CFG1_WM;
-#endif
 
-//	s3c_set_width_regs(this);
+	this->base = (void *) 0xe7100000;
+//	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+
+//	s3c_onenand_init(mtd);
 }