From: Dave Airlie <airlied@redhat.com>
Date: Tue, 28 Feb 2017 06:26:55 +0000 (+1000)
Subject: radv: fix txs for sampler buffers
X-Git-Tag: upstream/17.1.0~1865
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e66be3d3bb40160c7b7d57c596e4a25da168f1e6;p=platform%2Fupstream%2Fmesa.git

radv: fix txs for sampler buffers

I messed this up when I wrote it, this fixes:
dEQP-VK.memory.pipeline_barrier.*uniform_texel_buffer.*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index db7194c..a3310e1 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3625,7 +3625,7 @@ static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
 	}
 
 	if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
-		result = get_buffer_size(ctx, res_ptr, false);
+		result = get_buffer_size(ctx, res_ptr, true);
 		goto write_result;
 	}