From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Sat, 4 Mar 2023 18:16:54 +0000 (-0500)
Subject: asahi: Don't allow linear depth/stencil buffers
X-Git-Tag: upstream/23.3.3~11834
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e61d6540e63b7866812b89264e4329e1ad3a9664;p=platform%2Fupstream%2Fmesa.git

asahi: Don't allow linear depth/stencil buffers

We don't have a way to tell the ZLS hardware to use linear buffers, so if a
buffer could be used for depth/stencil, we have to twiddle. This isn't a problem
in practice, since depth/stencil buffers can't be shared across processes or
mapped directly as linear.

Fixes faults in depthstencil-render-miplevels, which was picking linear for one
buffer because of a STAGING bind flag. But that won't work :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21753>
---

diff --git a/src/gallium/drivers/asahi/agx_pipe.c b/src/gallium/drivers/asahi/agx_pipe.c
index 077c8d4..20d3360 100644
--- a/src/gallium/drivers/asahi/agx_pipe.c
+++ b/src/gallium/drivers/asahi/agx_pipe.c
@@ -289,6 +289,10 @@ agx_linear_allowed(const struct agx_resource *pres)
    if (pres->base.last_level != 0)
       return false;
 
+   /* Depth/stencil buffers must not be linear */
+   if (pres->base.bind & PIPE_BIND_DEPTH_STENCIL)
+      return false;
+
    switch (pres->base.target) {
    /* 1D is always linear */
    case PIPE_BUFFER: