From: Marek Olšák Date: Tue, 7 Nov 2017 15:12:56 +0000 (+0100) Subject: radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven only X-Git-Tag: upstream/18.1.0~4456 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e616743dabe4cdee789c7ad8386fbe9195cbb0ca;p=platform%2Fupstream%2Fmesa.git radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven only Reviewed-by: Nicolai Hähnle --- diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index b17828e..994ed58 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1405,11 +1405,11 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) if (!si_upload_vertex_buffer_descriptors(sctx)) return; - /* GFX9 scissor bug workaround. This must be done before VPORT scissor - * registers are changed. There is also a more efficient but more - * involved alternative workaround. + /* Vega10/Raven scissor bug workaround. This must be done before VPORT + * scissor registers are changed. There is also a more efficient but + * more involved alternative workaround. */ - if (sctx->b.chip_class == GFX9 && + if ((sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN) && si_is_atom_dirty(sctx, &sctx->scissors.atom)) { sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH; si_emit_cache_flush(sctx);