From: Alex Deucher <alexdeucher@gmail.com>
Date: Mon, 13 Dec 2010 04:27:23 +0000 (-0500)
Subject: drm/radeon/kms: disable ss fixed ref divide
X-Git-Tag: v3.12-rc1~7918^2~10
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e5fd205f28f83b3514dc5049b2d1388b10065a6d;p=kernel%2Fkernel-generic.git

drm/radeon/kms: disable ss fixed ref divide

Seems to cause problems on certain laptops

Fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=24462

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Tested-by: Luca Tettamanti <kronos.it@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index df2b6f2..3ed27ad 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -530,7 +530,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 					dp_clock = dig_connector->dp_clock;
 				}
 			}
-
+#if 0 /* doesn't work properly on some laptops */
 			/* use recommended ref_div for ss */
 			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 				if (ss_enabled) {
@@ -540,7 +540,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 					}
 				}
 			}
-
+#endif
 			if (ASIC_IS_AVIVO(rdev)) {
 				/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 				if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)