From: Pat Gavlin <pagavlin@microsoft.com>
Date: Thu, 23 Feb 2017 18:39:10 +0000 (-0800)
Subject: Address PR feedback.
X-Git-Tag: submit/tizen/20210909.063632~11030^2~7986^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e547aae4626955abbcd50278603c646715e332dd;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

Address PR feedback.


Commit migrated from https://github.com/dotnet/coreclr/commit/bd4028154190a245f322d859484fd39375201d00
---

diff --git a/src/coreclr/src/jit/codegencommon.cpp b/src/coreclr/src/jit/codegencommon.cpp
index 68b5820..0c4cba40 100644
--- a/src/coreclr/src/jit/codegencommon.cpp
+++ b/src/coreclr/src/jit/codegencommon.cpp
@@ -9451,9 +9451,16 @@ void CodeGen::genFnEpilog(BasicBlock* block)
 #endif // !FEATURE_STACK_FP_X87
 
 #ifdef JIT32_GCENCODER
-    // On IA32, we start the OS-reported portion of the epilog after restoring any callee-saved
-    // floating-point registers. This avoids the need to update the x86 unwinder and retains binary
-    // compatibility between later versions of the JIT and earlier versions of the runtime.
+    // When using the JIT32 GC encoder, we do not start the OS-reported portion of the epilog until after
+    // the above call to `genRestoreCalleeSavedFltRegs` because that function
+    //   a) does not actually restore any registers: there are none when targeting the Windows x86 ABI,
+    //      which is the only target that uses the JIT32 GC encoder
+    //   b) may issue a `vzeroupper` instruction to eliminate AVX -> SSE transition penalties.
+    // Because the `vzeroupper` instruction is not recognized by the VM's unwinder and there are no
+    // callee-save FP restores that the unwinder would need to see, we can avoid the need to change the
+    // unwinder (and break binary compat with older versions of the runtime) by starting the epilog
+    // after any `vzeroupper` instruction has been emitted. If either of the above conditions changes,
+    // we will need to rethink this.
     getEmitter()->emitStartEpilog();
 #endif
 
diff --git a/src/coreclr/src/jit/emit.cpp b/src/coreclr/src/jit/emit.cpp
index 8f92826..131fcfc 100644
--- a/src/coreclr/src/jit/emit.cpp
+++ b/src/coreclr/src/jit/emit.cpp
@@ -1983,22 +1983,14 @@ void emitter::emitEndFnEpilog()
 #ifdef JIT32_GCENCODER
     assert(emitEpilogLast != nullptr);
 
-    UNATIVE_OFFSET newSize;
     UNATIVE_OFFSET epilogBegCodeOffset = emitEpilogLast->elLoc.CodeOffset(this);
-#ifdef _TARGET_XARCH_
     UNATIVE_OFFSET epilogExitSeqStartCodeOffset = emitExitSeqBegLoc.CodeOffset(this);
-#else
-    UNATIVE_OFFSET epilogExitSeqStartCodeOffset = emitCodeOffset(emitCurIG, emitCurOffset());
-#endif
-
-    newSize = epilogExitSeqStartCodeOffset - epilogBegCodeOffset;
-
-#ifdef _TARGET_X86_
+    UNATIVE_OFFSET newSize = epilogExitSeqStartCodeOffset - epilogBegCodeOffset;
 
     /* Compute total epilog size */
-
     assert(emitEpilogSize == 0 || emitEpilogSize == newSize); // All epilogs must be identical
-    emitEpilogSize                     = newSize;
+    emitEpilogSize = newSize;
+
     UNATIVE_OFFSET epilogEndCodeOffset = emitCodeOffset(emitCurIG, emitCurOffset());
     assert(epilogExitSeqStartCodeOffset != epilogEndCodeOffset);
 
@@ -2018,8 +2010,6 @@ void emitter::emitEndFnEpilog()
                );
         emitExitSeqSize = newSize;
     }
-
-#endif // _TARGET_X86_
 #endif // JIT32_GCENCODER
 }