From: Kenneth Graunke Date: Fri, 9 Sep 2016 06:48:51 +0000 (-0700) Subject: i965: Introduce downcast helpers for prog_data structures. X-Git-Tag: upstream/17.1.0~5929 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e51e055fcdf8107aafaba358fa65b00f963e1728;p=platform%2Fupstream%2Fmesa.git i965: Introduce downcast helpers for prog_data structures. Similar to brw_context(...), intel_texture_object(...), and so on. Signed-off-by: Kenneth Graunke Reviewed-by: Timothy Arceri --- diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h index 445c166..447d05b 100644 --- a/src/mesa/drivers/dri/i965/brw_compiler.h +++ b/src/mesa/drivers/dri/i965/brw_compiler.h @@ -731,6 +731,23 @@ struct brw_gs_prog_data unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */]; }; +#define DEFINE_PROG_DATA_DOWNCAST(stage) \ +static inline struct brw_##stage##_prog_data * \ +brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \ +{ \ + return (struct brw_##stage##_prog_data *) prog_data; \ +} +DEFINE_PROG_DATA_DOWNCAST(vue) +DEFINE_PROG_DATA_DOWNCAST(vs) +DEFINE_PROG_DATA_DOWNCAST(tcs) +DEFINE_PROG_DATA_DOWNCAST(tes) +DEFINE_PROG_DATA_DOWNCAST(gs) +DEFINE_PROG_DATA_DOWNCAST(wm) +DEFINE_PROG_DATA_DOWNCAST(cs) +DEFINE_PROG_DATA_DOWNCAST(ff_gs) +DEFINE_PROG_DATA_DOWNCAST(clip) +DEFINE_PROG_DATA_DOWNCAST(sf) +#undef DEFINE_PROG_DATA_DOWNCAST /** @} */ diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 58f5415..1c7a6e6 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1125,7 +1125,7 @@ void fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos) { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data; + struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data); assert(dst.type == BRW_REGISTER_TYPE_F); if (wm_prog_data->persample_dispatch) { @@ -1293,7 +1293,7 @@ fs_reg * fs_visitor::emit_samplemaskin_setup() { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data; + struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data); assert(devinfo->gen >= 6); fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type)); @@ -1344,7 +1344,7 @@ fs_visitor::resolve_source_modifiers(const fs_reg &src) void fs_visitor::emit_discard_jump() { - assert(((brw_wm_prog_data*) this->prog_data)->uses_kill); + assert(brw_wm_prog_data(this->prog_data)->uses_kill); /* For performance, after a discard, jump to the end of the * shader if all relevant channels have been discarded. @@ -1361,8 +1361,7 @@ fs_visitor::emit_gs_thread_end() { assert(stage == MESA_SHADER_GEOMETRY); - struct brw_gs_prog_data *gs_prog_data = - (struct brw_gs_prog_data *) prog_data; + struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); if (gs_compile->control_data_header_size_bits > 0) { emit_gs_control_data_bits(this->final_gs_vertex_count); @@ -1451,7 +1450,7 @@ void fs_visitor::calculate_urb_setup() { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; memset(prog_data->urb_setup, -1, @@ -1542,7 +1541,7 @@ void fs_visitor::assign_urb_setup() { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); int urb_start = payload.num_regs + prog_data->base.curb_read_length; @@ -1609,7 +1608,7 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst) void fs_visitor::assign_vs_urb_setup() { - brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data; + struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(prog_data); assert(stage == MESA_SHADER_VERTEX); @@ -1640,7 +1639,7 @@ fs_visitor::assign_tes_urb_setup() { assert(stage == MESA_SHADER_TESS_EVAL); - brw_vue_prog_data *vue_prog_data = (brw_vue_prog_data *) prog_data; + struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data); first_non_payload_grf += 8 * vue_prog_data->urb_read_length; @@ -1655,7 +1654,7 @@ fs_visitor::assign_gs_urb_setup() { assert(stage == MESA_SHADER_GEOMETRY); - brw_vue_prog_data *vue_prog_data = (brw_vue_prog_data *) prog_data; + struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data); first_non_payload_grf += 8 * vue_prog_data->urb_read_length * nir->info.gs.vertices_in; @@ -1940,7 +1939,7 @@ fs_visitor::assign_constant_locations() int thread_local_id_index = (stage == MESA_SHADER_COMPUTE) ? - ((brw_cs_prog_data*)stage_prog_data)->thread_local_id_index : -1; + brw_cs_prog_data(stage_prog_data)->thread_local_id_index : -1; /* First, we walk through the instructions and do two things: * @@ -2085,7 +2084,7 @@ fs_visitor::assign_constant_locations() ralloc_free(param); if (stage == MESA_SHADER_COMPUTE) - ((brw_cs_prog_data*)stage_prog_data)->thread_local_id_index = + brw_cs_prog_data(stage_prog_data)->thread_local_id_index = new_thread_local_id_index; } @@ -3597,7 +3596,7 @@ setup_color_payload(const fs_builder &bld, const brw_wm_prog_key *key, static void lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, - const brw_wm_prog_data *prog_data, + const struct brw_wm_prog_data *prog_data, const brw_wm_prog_key *key, const fs_visitor::thread_payload &payload) { @@ -4353,7 +4352,7 @@ fs_visitor::lower_logical_sends() case FS_OPCODE_FB_WRITE_LOGICAL: assert(stage == MESA_SHADER_FRAGMENT); lower_fb_write_logical_send(ibld, inst, - (const brw_wm_prog_data *)prog_data, + brw_wm_prog_data(prog_data), (const brw_wm_prog_key *)key, payload); break; @@ -5432,7 +5431,7 @@ void fs_visitor::setup_fs_payload_gen6() { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); assert(devinfo->gen >= 6); @@ -5531,10 +5530,8 @@ fs_visitor::setup_gs_payload() { assert(stage == MESA_SHADER_GEOMETRY); - struct brw_gs_prog_data *gs_prog_data = - (struct brw_gs_prog_data *) prog_data; - struct brw_vue_prog_data *vue_prog_data = - (struct brw_vue_prog_data *) prog_data; + struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); + struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data); /* R0: thread header, R1: output URB handles */ payload.num_regs = 2; @@ -5942,8 +5939,7 @@ fs_visitor::run_tcs_single_patch() { assert(stage == MESA_SHADER_TESS_CTRL); - struct brw_tcs_prog_data *tcs_prog_data = - (struct brw_tcs_prog_data *) prog_data; + struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data); /* r1-r4 contain the ICP handles. */ payload.num_regs = 5; @@ -6104,7 +6100,7 @@ fs_visitor::run_gs() bool fs_visitor::run_fs(bool allow_spilling, bool do_rep_send) { - brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data; + struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data); brw_wm_prog_key *wm_key = (brw_wm_prog_key *) this->key; assert(stage == MESA_SHADER_FRAGMENT); @@ -6598,8 +6594,7 @@ static void cs_fill_push_const_info(const struct gen_device_info *devinfo, struct brw_cs_prog_data *cs_prog_data) { - const struct brw_stage_prog_data *prog_data = - (struct brw_stage_prog_data*) cs_prog_data; + const struct brw_stage_prog_data *prog_data = &cs_prog_data->base; bool fill_thread_id = cs_prog_data->thread_local_id_index >= 0 && cs_prog_data->thread_local_id_index < (int)prog_data->nr_params; diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h b/src/mesa/drivers/dri/i965/brw_fs_builder.h index bae151c..e8cbb9c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_builder.h +++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h @@ -240,7 +240,7 @@ namespace brw { group() + dispatch_width() <= 16); if (shader->stage != MESA_SHADER_FRAGMENT) { return brw_imm_d(0xffffffff); - } else if (((brw_wm_prog_data *)shader->stage_prog_data)->uses_kill) { + } else if (brw_wm_prog_data(shader->stage_prog_data)->uses_kill) { return brw_flag_reg(0, 1); } else { return retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD); diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 842e125..d7b5cc6 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -198,7 +198,7 @@ fs_generator::fire_fb_write(fs_inst *inst, { uint32_t msg_control; - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); if (devinfo->gen < 6) { brw_push_insn_state(p); @@ -246,7 +246,7 @@ fs_generator::fire_fb_write(fs_inst *inst, void fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) { - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key; struct brw_reg implied_header; @@ -357,8 +357,7 @@ fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload) { assert(inst->size_written % REG_SIZE == 0); - brw_wm_prog_data *prog_data = - reinterpret_cast(this->prog_data); + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); const unsigned surf_index = prog_data->binding_table.render_target_start + inst->target; diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 54b9398..4e68ffb 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -1637,7 +1637,7 @@ emit_pixel_interpolater_send(const fs_builder &bld, glsl_interp_mode interpolation) { struct brw_wm_prog_data *wm_prog_data = - (struct brw_wm_prog_data *) bld.shader->stage_prog_data; + brw_wm_prog_data(bld.shader->stage_prog_data); fs_inst *inst; fs_reg payload; int mlen; @@ -1683,8 +1683,7 @@ fs_visitor::emit_gs_end_primitive(const nir_src &vertex_count_nir_src) { assert(stage == MESA_SHADER_GEOMETRY); - struct brw_gs_prog_data *gs_prog_data = - (struct brw_gs_prog_data *) prog_data; + struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); if (gs_compile->control_data_header_size_bits == 0) return; @@ -1745,8 +1744,7 @@ fs_visitor::emit_gs_control_data_bits(const fs_reg &vertex_count) assert(stage == MESA_SHADER_GEOMETRY); assert(gs_compile->control_data_bits_per_vertex != 0); - struct brw_gs_prog_data *gs_prog_data = - (struct brw_gs_prog_data *) prog_data; + struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); const fs_builder abld = bld.annotate("emit control data bits"); const fs_builder fwa_bld = bld.exec_all(); @@ -1901,8 +1899,7 @@ fs_visitor::emit_gs_vertex(const nir_src &vertex_count_nir_src, { assert(stage == MESA_SHADER_GEOMETRY); - struct brw_gs_prog_data *gs_prog_data = - (struct brw_gs_prog_data *) prog_data; + struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); fs_reg vertex_count = get_nir_src(vertex_count_nir_src); vertex_count.type = BRW_REGISTER_TYPE_UD; @@ -2000,7 +1997,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst, unsigned num_components, unsigned first_component) { - struct brw_gs_prog_data *gs_prog_data = (struct brw_gs_prog_data *) prog_data; + struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data); nir_const_value *vertex_const = nir_src_as_const_value(vertex_src); nir_const_value *offset_const = nir_src_as_const_value(offset_src); @@ -2357,8 +2354,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld, { assert(stage == MESA_SHADER_TESS_CTRL); struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) key; - struct brw_tcs_prog_data *tcs_prog_data = - (struct brw_tcs_prog_data *) prog_data; + struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data); fs_reg dst; if (nir_intrinsic_infos[instr->intrinsic].has_dest) @@ -2874,7 +2870,7 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr) { assert(stage == MESA_SHADER_TESS_EVAL); - struct brw_tes_prog_data *tes_prog_data = (struct brw_tes_prog_data *) prog_data; + struct brw_tes_prog_data *tes_prog_data = brw_tes_prog_data(prog_data); fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) @@ -3078,7 +3074,7 @@ fs_visitor::nir_emit_gs_intrinsic(const fs_builder &bld, switch (instr->intrinsic) { case nir_intrinsic_load_primitive_id: assert(stage == MESA_SHADER_GEOMETRY); - assert(((struct brw_gs_prog_data *)prog_data)->include_primitive_id); + assert(brw_gs_prog_data(prog_data)->include_primitive_id); bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD)); break; @@ -3154,8 +3150,8 @@ fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, const brw_wm_prog_key *wm_key = reinterpret_cast(key); assert(!wm_key->coherent_fb_fetch); - const brw_wm_prog_data *wm_prog_data = - reinterpret_cast(stage_prog_data); + const struct brw_wm_prog_data *wm_prog_data = + brw_wm_prog_data(stage_prog_data); /* Calculate the surface index relative to the start of the texture binding * table block, since that's what the texturing messages expect. @@ -3599,8 +3595,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr) { assert(stage == MESA_SHADER_COMPUTE); - struct brw_cs_prog_data *cs_prog_data = - (struct brw_cs_prog_data *) prog_data; + struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data); fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) @@ -3804,7 +3799,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr case nir_intrinsic_atomic_counter_comp_swap: { if (stage == MESA_SHADER_FRAGMENT && instr->intrinsic != nir_intrinsic_atomic_counter_read) - ((struct brw_wm_prog_data *)prog_data)->has_side_effects = true; + brw_wm_prog_data(prog_data)->has_side_effects = true; /* Get some metadata from the image intrinsic. */ const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic]; @@ -3852,7 +3847,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr if (stage == MESA_SHADER_FRAGMENT && instr->intrinsic != nir_intrinsic_image_load) - ((struct brw_wm_prog_data *)prog_data)->has_side_effects = true; + brw_wm_prog_data(prog_data)->has_side_effects = true; /* Get the referenced image variable and type. */ const nir_variable *var = instr->variables[0]->var; @@ -4163,7 +4158,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr assert(devinfo->gen >= 7); if (stage == MESA_SHADER_FRAGMENT) - ((struct brw_wm_prog_data *)prog_data)->has_side_effects = true; + brw_wm_prog_data(prog_data)->has_side_effects = true; /* Block index */ fs_reg surf_index; @@ -4371,7 +4366,7 @@ fs_visitor::nir_emit_ssbo_atomic(const fs_builder &bld, int op, nir_intrinsic_instr *instr) { if (stage == MESA_SHADER_FRAGMENT) - ((struct brw_wm_prog_data *)prog_data)->has_side_effects = true; + brw_wm_prog_data(prog_data)->has_side_effects = true; fs_reg dest; if (nir_intrinsic_infos[instr->intrinsic].has_dest) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index e96a3e8..0efd68f 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -39,7 +39,7 @@ fs_visitor::emit_vs_system_value(int location) fs_reg(ATTR, 4 * (_mesa_bitcount_64(nir->info.inputs_read) + _mesa_bitcount_64(nir->info.double_inputs_read)), BRW_REGISTER_TYPE_D); - brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data; + struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(prog_data); switch (location) { case SYSTEM_VALUE_BASE_VERTEX: @@ -160,7 +160,7 @@ fs_visitor::emit_dummy_fs() /* Tell the SF we don't have any inputs. Gen4-5 require at least one * varying to avoid GPU hangs, so set that. */ - brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data; + struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data); wm_prog_data->num_varying_inputs = devinfo->gen < 6 ? 1 : 0; memset(wm_prog_data->urb_setup, -1, sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX); @@ -184,7 +184,7 @@ struct brw_reg fs_visitor::interp_reg(int location, int channel) { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); int regnr = prog_data->urb_setup[location] * 2 + channel / 2; int stride = (channel & 1) * 4; @@ -308,7 +308,7 @@ fs_visitor::emit_interpolation_setup_gen6() this->wpos_w = vgrf(glsl_type::float_type); abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); - brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) prog_data; + struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data); uint32_t centroid_modes = wm_prog_data->barycentric_interp_modes & (1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID | 1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID); @@ -406,7 +406,7 @@ fs_visitor::emit_single_fb_write(const fs_builder &bld, fs_reg src0_alpha, unsigned components) { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); /* Hand over gl_FragDepth or the payload depth. */ const fs_reg dst_depth = (payload.dest_depth_reg ? @@ -445,7 +445,7 @@ void fs_visitor::emit_fb_writes() { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; fs_inst *inst = NULL; @@ -533,8 +533,7 @@ fs_visitor::setup_uniform_clipplane_values(gl_clip_plane *clip_planes) */ void fs_visitor::compute_clip_distance(gl_clip_plane *clip_planes) { - struct brw_vue_prog_data *vue_prog_data = - (struct brw_vue_prog_data *) prog_data; + struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data); const struct brw_vs_prog_key *key = (const struct brw_vs_prog_key *) this->key; @@ -590,7 +589,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) int slot, urb_offset, length; int starting_urb_offset = 0; const struct brw_vue_prog_data *vue_prog_data = - (const struct brw_vue_prog_data *) this->prog_data; + brw_vue_prog_data(this->prog_data); const struct brw_vs_prog_key *vs_key = (const struct brw_vs_prog_key *) this->key; const GLbitfield64 psiz_mask = @@ -639,7 +638,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) if (stage == MESA_SHADER_GEOMETRY) { const struct brw_gs_prog_data *gs_prog_data = - (const struct brw_gs_prog_data *) this->prog_data; + brw_gs_prog_data(this->prog_data); /* We need to increment the Global Offset to skip over the control data * header and the extra "Vertex Count" field (1 HWord) at the beginning @@ -901,8 +900,7 @@ fs_visitor::init() } if (stage == MESA_SHADER_COMPUTE) { - const brw_cs_prog_data *cs_prog_data = - (const brw_cs_prog_data *) prog_data; + const struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data); unsigned size = cs_prog_data->local_size[0] * cs_prog_data->local_size[1] * cs_prog_data->local_size[2]; diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp index bfd14f2..8f4c1cf 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp +++ b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp @@ -123,7 +123,7 @@ static const struct { void fs_visitor::setup_fs_payload_gen4() { assert(stage == MESA_SHADER_FRAGMENT); - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; GLuint reg = 2; bool kill_stats_promoted_workaround = false;