From: Jessica Paquette <jpaquette@apple.com>
Date: Tue, 23 Apr 2019 17:17:06 +0000 (+0000)
Subject: [AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode
X-Git-Tag: llvmorg-10-init~7210
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e50e6d256375b47efb30a6f9f1fe795f7d95a8a3;p=platform%2Fupstream%2Fllvm.git

[AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode

Noticed an unnecessary fallback in arm64-vmul caused by this.

Also add a regbankselect test for G_FMA.

llvm-svn: 359013
---

diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index 2872518..025f2381 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -389,6 +389,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
   case TargetOpcode::G_FADD:
   case TargetOpcode::G_FSUB:
   case TargetOpcode::G_FMUL:
+  case TargetOpcode::G_FMA:
   case TargetOpcode::G_FDIV:
   case TargetOpcode::G_FCONSTANT:
   case TargetOpcode::G_FPEXT:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
new file mode 100644
index 0000000..7048223
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
+
+...
+---
+
+name:            fma_f32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $s0, $s1, $s2
+
+    ; CHECK-LABEL: name: fma_f32
+    ; CHECK: liveins: $s0, $s1, $s2
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s1
+    ; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s2
+    ; CHECK: %3:fpr(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: $s0 = COPY %3(s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %0:_(s32) = COPY $s0
+    %1:_(s32) = COPY $s1
+    %2:_(s32) = COPY $s2
+    %3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
+    $s0 = COPY %3(s32)
+    RET_ReallyLR implicit $s0
+
+...
+---
+name:            fma_f64
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $d0, $d1, $d2
+
+    ; CHECK-LABEL: name: fma_f64
+    ; CHECK: liveins: $d0, $d1, $d2
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d1
+    ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d2
+    ; CHECK: %3:fpr(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: $d0 = COPY %3(s64)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %0:_(s64) = COPY $d0
+    %1:_(s64) = COPY $d1
+    %2:_(s64) = COPY $d2
+    %3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
+    $d0 = COPY %3(s64)
+    RET_ReallyLR implicit $d0
+
+...