From: Tapani Pälli <tapani.palli@intel.com>
Date: Mon, 24 Apr 2023 10:11:48 +0000 (+0300)
Subject: anv: implement state cache invalidate for Wa_16013063087
X-Git-Tag: upstream/23.3.3~9555
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e501b31e159d3b4e7ced3263a219f25a44cb02d0;p=platform%2Fupstream%2Fmesa.git

anv: implement state cache invalidate for Wa_16013063087

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>
---

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index fe3f7e66567..9d3aee90f77 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -6556,6 +6556,17 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
            ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
 #endif
 
+   /* Wa_16013063087 -  State Cache Invalidate must be issued prior to
+    * PIPELINE_SELECT when switching from 3D to Compute.
+    *
+    * SW must do this by programming of PIPECONTROL with “CS Stall” followed by
+    * a PIPECONTROL with State Cache Invalidate bit set.
+    *
+    */
+   if (cmd_buffer->state.current_pipeline == _3D && pipeline == GPGPU &&
+       intel_needs_workaround(cmd_buffer->device->info, 16013063087))
+      bits |= ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
+
    anv_add_pending_pipe_bits(cmd_buffer, bits, "flush/invalidate PIPELINE_SELECT");
    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);