From: Jay Foad Date: Thu, 23 Sep 2021 07:24:28 +0000 (+0100) Subject: [LiveIntervals] Repair live intervals that gain subranges X-Git-Tag: upstream/15.0.7~30617 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e4e95f14f15aceb2641c2b917eca58aaf988c4a7;p=platform%2Fupstream%2Fllvm.git [LiveIntervals] Repair live intervals that gain subranges In repairIntervalsInRange, if the new instructions refer to subregs but the old instructions did not, make sure any existing live interval for the superreg is updated to have subranges. Also skip repairing any range that we have recalculated from scratch, partly for efficiency but also to avoids some cases that repairOldRegInRange can't handle. The existing test/CodeGen/AMDGPU/twoaddr-regsequence.mir provides some test coverage for this change: when TwoAddressInstructionPass converts REG_SEQUENCE into subreg copies, the live intervals will now get subranges and MachineVerifier will verify that the subranges are correct. Unfortunately MachineVerifier does not complain if the subranges are not present, so the test also passed before this patch. This patch also fixes ~800 of the ~1500 failures in the whole CodeGen lit test suite when -early-live-intervals is forced on. Differential Revision: https://reviews.llvm.org/D110328 --- diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp index ac6818a..a4dd71c 100644 --- a/llvm/lib/CodeGen/LiveIntervals.cpp +++ b/llvm/lib/CodeGen/LiveIntervals.cpp @@ -1677,6 +1677,8 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB, Indexes->repairIndexesInRange(MBB, Begin, End); + // Make sure a live interval exists for all register operands in the range. + SmallVector RegsToRepair(OrigRegs.begin(), OrigRegs.end()); for (MachineBasicBlock::iterator I = End; I != Begin;) { --I; MachineInstr &MI = *I; @@ -1685,14 +1687,25 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB, for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(), MOE = MI.operands_end(); MOI != MOE; ++MOI) { - if (MOI->isReg() && Register::isVirtualRegister(MOI->getReg()) && - !hasInterval(MOI->getReg())) { - createAndComputeVirtRegInterval(MOI->getReg()); + if (MOI->isReg() && MOI->getReg().isVirtual()) { + Register Reg = MOI->getReg(); + // If the new instructions refer to subregs but the old instructions did + // not, throw away any old live interval so it will be recomputed with + // subranges. + if (MOI->getSubReg() && hasInterval(Reg) && + !getInterval(Reg).hasSubRanges() && + MRI->shouldTrackSubRegLiveness(Reg)) + removeInterval(Reg); + if (!hasInterval(Reg)) { + createAndComputeVirtRegInterval(Reg); + // Don't bother to repair a freshly calculated live interval. + erase_value(RegsToRepair, Reg); + } } } } - for (Register Reg : OrigRegs) { + for (Register Reg : RegsToRepair) { if (!Reg.isVirtual()) continue; diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll index e5321c8..c7b7fc4 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s +; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 -early-live-intervals -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s define weak_odr amdgpu_kernel void @test_mul24_knownbits_kernel(float addrspace(1)* %p) #4 { ; GCN-LABEL: test_mul24_knownbits_kernel: diff --git a/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll b/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll index 7c3f73d..a622d18 100644 --- a/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Thumb2/mve-ctlz.ll b/llvm/test/CodeGen/Thumb2/mve-ctlz.ll index eee41da..4b92a9c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ctlz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ctlz.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -early-live-intervals -verify-machineinstrs -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){ ; CHECK-LABEL: ctlz_2i64_0_t: