From: Arnold Schwaighofer <aschwaighofer@apple.com>
Date: Tue, 19 Feb 2013 20:16:45 +0000 (+0000)
Subject: ARM NEON: Don't need COPY_TO_REGCLASS in pattern
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e4df5eb34a47207941f53787c48dff20f1b4ff65;p=platform%2Fupstream%2Fllvm.git

ARM NEON: Don't need COPY_TO_REGCLASS in pattern

In my previous commit:
"Merge a f32 bitcast of a v2i32 extractelt

A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers."

I added a pattern containing a copy_to_regclass. The copy_to_regclass is
actually not needed.

radar://13191881

llvm-svn: 175555
---

diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index 9f68c22..0411ac4 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -5747,9 +5747,7 @@ def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
 
 // Fold extracting an element out of a v2i32 into a vfp register.
 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
-          (f32 (EXTRACT_SUBREG
-                (v2f32 (COPY_TO_REGCLASS (v2i32 DPR:$src), DPR)),
-                (SSubReg_f32_reg imm:$lane)))>;
+          (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
 
 // Vector lengthening move with load, matching extending loads.