From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Thu, 24 Aug 2017 13:48:26 +0000 (+0200)
Subject: arm: dts: sun8i: a83t: Add the UART1 controller
X-Git-Tag: v4.19~2159^2~6^2~63
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e488af71aa6704f327de6a7df7ae91df8f2997a0;p=platform%2Fkernel%2Flinux-rpi.git

arm: dts: sun8i: a83t: Add the UART1 controller

The A83T has an UART1 controller, with the RTS and CTS pins routed so it
can be used for devices with hardware flow control, like a bluetooth chip.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 91dee79..a9032c2 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -373,6 +373,16 @@
 				pins = "PF2", "PF4";
 				function = "uart0";
 			};
+
+			uart1_pins: uart1-pins {
+				pins = "PG6", "PG7";
+				function = "uart1";
+			};
+
+			uart1_rts_cts_pins: uart1-rts-cts-pins {
+				pins = "PG8", "PG9";
+				function = "uart1";
+			};
 		};
 
 		timer@1c20c00 {
@@ -417,6 +427,17 @@
 			status = "disabled";
 		};
 
+		uart1: serial@01c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@1c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,