From: Dmitry Preobrazhensky <d-pre@mail.ru>
Date: Tue, 26 Jul 2022 14:48:25 +0000 (+0300)
Subject: [AMDGPU][MC][GFX11] Correct src0 for VOP3_DPP variants of v_cmp*class* opcodes
X-Git-Tag: upstream/15.0.7~395
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e43621b09c9741d2e3a8a3d8ed216699af5ff8ba;p=platform%2Fupstream%2Fllvm.git

[AMDGPU][MC][GFX11] Correct src0 for VOP3_DPP variants of v_cmp*class* opcodes

Disable SGPRs for src0 of these opcodes.

Differential Revision: https://reviews.llvm.org/D130486
---

diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index d489a08..5973d32 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -718,7 +718,7 @@ class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType vt> :
   // DPP8 forbids modifiers and can inherit from VOPC_Profile
 
   let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
-  dag InsPartVOP3DPP = (ins Src0Mod:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1);
+  dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1);
   let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel),
                                                        (ins)));
   let Asm64 = "$sdst, $src0_modifiers, $src1";
diff --git a/llvm/test/MC/AMDGPU/gfx11_err.s b/llvm/test/MC/AMDGPU/gfx11_err.s
index 82ebbb2..2d1cfe2 100644
--- a/llvm/test/MC/AMDGPU/gfx11_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_err.s
@@ -77,3 +77,9 @@ v_dot4_i32_i8 v0, v1, v2, v3
 
 v_dot4c_i32_i8 v0, v1, v2
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+v_cmp_class_f16_e64_dpp s105, s2, v2 row_ror:15
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_class_f32_e64_dpp s1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction