From: Philip Reames <preames@rivosinc.com>
Date: Thu, 22 Sep 2022 15:27:23 +0000 (-0700)
Subject: [RISCV] Verify consistency of a couple TSFlags related to vector operands
X-Git-Tag: upstream/17.0.6~32768
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e41765aa4dc034ca582d2d1df7944c1c1b3a9ba7;p=platform%2Fupstream%2Fllvm.git

[RISCV] Verify consistency of a couple TSFlags related to vector operands

Various bits of existing code assume the presence of one operand implies the presence of another.  Add verifier rules to catch violations.

Differential Revision: https://reviews.llvm.org/D133810
---

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 1afd2fb..98ae360 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1237,6 +1237,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         return false;
       }
     }
+    if (!RISCVII::hasSEWOp(TSFlags)) {
+      ErrInfo = "VL operand w/o SEW operand?";
+      return false;
+    }
   }
   if (RISCVII::hasSEWOp(TSFlags)) {
     unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
@@ -1258,6 +1262,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
       ErrInfo = "Invalid Policy Value";
       return false;
     }
+    if (!RISCVII::hasVLOp(TSFlags)) {
+      ErrInfo = "policy operand w/o VL operand?";
+      return false;
+    }
   }
 
   return true;