From: Kai Luo <lkail@cn.ibm.com>
Date: Wed, 30 Dec 2020 02:23:05 +0000 (+0000)
Subject: [PowerPC] Add mir test to show effect of `optimizeCompareInstr` when `equalityOnly... 
X-Git-Tag: llvmorg-13-init~2406
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e3e25cfb44bc2a35e3b53d62d37c27b7d13157b6;p=platform%2Fupstream%2Fllvm.git

[PowerPC] Add mir test to show effect of `optimizeCompareInstr` when `equalityOnly` is true. NFC.
---

diff --git a/llvm/test/CodeGen/PowerPC/peephole-cmp-eq.mir b/llvm/test/CodeGen/PowerPC/peephole-cmp-eq.mir
new file mode 100644
index 0000000..bac0a69
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/peephole-cmp-eq.mir
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=powerpc64le -simplify-mir -verify-machineinstrs \
+# RUN:   -run-pass=peephole-opt %s -o - | FileCheck %s
+# Test to show effect of `optimizeCompareInstr` when `equalityOnly` is true.
+---
+name:            h
+alignment:       16
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: g8rc }
+  - { id: 1, class: g8rc }
+  - { id: 2, class: g8rc_and_g8rc_nox0 }
+  - { id: 3, class: crrc }
+  - { id: 4, class: g8rc_and_g8rc_nox0 }
+  - { id: 5, class: g8rc }
+liveins:
+  - { reg: '$x3', virtual-reg: '%0' }
+  - { reg: '$x4', virtual-reg: '%1' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $x3, $x4
+
+    ; CHECK-LABEL: name: h
+    ; CHECK: liveins: $x3, $x4
+    ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x4
+    ; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x3
+    ; CHECK: [[SUBF8_rec:%[0-9]+]]:g8rc_and_g8rc_nox0 = SUBF8_rec [[COPY]], [[COPY1]], implicit-def $cr0
+    ; CHECK: [[COPY2:%[0-9]+]]:crrc = COPY killed $cr0
+    ; CHECK: [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 $zero8, [[SUBF8_rec]], [[COPY2]].sub_eq
+    ; CHECK: $x3 = COPY [[ISEL8_]]
+    ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
+    %1:g8rc = COPY $x4
+    %0:g8rc = COPY $x3
+    %2:g8rc_and_g8rc_nox0 = SUBF8 %1, %0
+    %3:crrc = CMPLD %0, %1
+    %4:g8rc_and_g8rc_nox0 = LI8 0
+    %5:g8rc = ISEL8 %4, %2, %3.sub_eq
+    $x3 = COPY %5
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+...