From: Rabin Vincent <rabin@rab.in>
Date: Thu, 1 May 2014 14:24:44 +0000 (+0100)
Subject: armv7m_nvic: fix CPUID Base Register
X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~871^2~8
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e3da9921ebc554fad3224a9fdda9a7425ffd9ef7;p=sdk%2Femulator%2Fqemu.git

armv7m_nvic: fix CPUID Base Register

cp15.c0_cpuid is never initialized for ARMv7-M; take the value directly
from cpu->midr instead.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Message-id: 1398036308-32166-1-git-send-email-rabin@rab.in
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 6066fa6..f5b0c3b 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -173,7 +173,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
         return 10000;
     case 0xd00: /* CPUID Base.  */
         cpu = ARM_CPU(current_cpu);
-        return cpu->env.cp15.c0_cpuid;
+        return cpu->midr;
     case 0xd04: /* Interrupt Control State.  */
         /* VECTACTIVE */
         val = s->gic.running_irq[0];