From: Anup Patel Date: Mon, 14 Nov 2022 09:05:34 +0000 (+0530) Subject: RISC-V: Fix MEMREMAP_WB for systems with Svpbmt X-Git-Tag: v6.1.8~1286 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=e395fdfec46d4adbee0e849e9feaa706871da2af;p=platform%2Fkernel%2Flinux-starfive.git RISC-V: Fix MEMREMAP_WB for systems with Svpbmt [ Upstream commit b91676fc16cd384a81e3af52c641aa61985cc231 ] Currently, the memremap() called with MEMREMAP_WB maps memory using the generic ioremap() function which breaks on system with Svpbmt because memory mapped using _PAGE_IOREMAP page attributes is treated as strongly-ordered non-cacheable IO memory. To address this, we implement RISC-V specific arch_memremap_wb() which maps memory using _PAGE_KERNEL page attributes resulting in write-back cacheable mapping on systems with Svpbmt. Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20221114090536.1662624-2-apatel@ventanamicro.com Signed-off-by: Palmer Dabbelt Signed-off-by: Sasha Levin --- diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 92080a2..42497d4 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -135,4 +135,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #include +#ifdef CONFIG_MMU +#define arch_memremap_wb(addr, size) \ + ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL)) +#endif + #endif /* _ASM_RISCV_IO_H */